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公开(公告)号：US09793885B2
公开(公告)日：2017-10-17
申请号：US15340430
申请日：2016-11-01
Applicant: Tensorcom, Inc.
Inventor： Dai Dai
CPC classification number: H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.
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2.发明申请Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators 有权用于消除比较器的输入电容的有源负电容电路的方法和装置公开(公告)号：US20150207517A1
公开(公告)日：2015-07-23
申请号：US14672214
申请日：2015-03-29
Applicant: Tensorcom, Inc.
Inventor： Dai Dai
CPC classification number: H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.
Abstract translation: 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器和差分金属层迹线的输入差分栅极电容加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 该取消扩展了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS组成，其中电容器连接其源极，其中每个NMOS由电流源偏置。
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3.发明申请公开(公告)号：US20190222208A1
公开(公告)日：2019-07-18
申请号：US16231268
申请日：2018-12-21
Applicant: TensorCom, Inc.
Inventor： Dai Dai
CPC classification number: H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier
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4.发明授权Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators 有权用于消除比较器的输入电容的有源负电容电路的方法和装置公开(公告)号：US09484941B2
公开(公告)日：2016-11-01
申请号：US14995471
申请日：2016-01-14
Applicant: Tensorcom, Inc.
Inventor： Dai Dai
CPC classification number: H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
Abstract: A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal.
Abstract translation: 负电容电路包括耦合到第一晶体管的漏极和第二晶体管的栅极的第一节点; 耦合到所述第二晶体管的漏极和所述第一晶体管的栅极的第二节点; 耦合在所述第一晶体管的源极和所述第二晶体管的源极之间的电容器; 耦合在电源电压和第一晶体管的源极之间的第一电流镜; 以及耦合在所述电源电压和所述第二晶体管的源极之间的第二电流镜。 电路可以被配置为在较短的时间段内驱动第一和第二节点之间的差分电容性负载，从而增加差分信号的传输带宽。
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Patent Agency Ranking
公开(公告)号：US10200024B2
公开(公告)日：2019-02-05
申请号：US15652934
申请日：2017-07-18
Applicant: Tensorcom, Inc.
Inventor： Dai Dai
Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.
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6.发明申请公开(公告)号：US20170317668A1
公开(公告)日：2017-11-02
申请号：US15652934
申请日：2017-07-18
Applicant: Tensorcom, Inc.
Inventor： Dai Dai
CPC classification number: H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier
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7.发明申请Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators 有权用于消除比较器的输入电容的有源负电容电路的方法和装置公开(公告)号：US20170063362A1
公开(公告)日：2017-03-02
申请号：US15340430
申请日：2016-11-01
Applicant: Tensorcom, Inc.
Inventor： Dai Dai
CPC classification number: H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier
Abstract translation: 电路包括耦合到第一和第二节点的第一放大器; 耦合到第一和第二节点的差分电容性负载，耦合在交叉耦合晶体管电路中的晶体管的漏极之间的差分电容性负载; 耦合到每个晶体管的源极的电流镜; 以及耦合在晶体管的源极之间的电容器。 多个放大器可以耦合到差分电容性负载，其中每个放大器包括比较器的无时钟前置放大器。 放大器可以彼此邻接，使得第一放大器中的第一差分级的有源晶体管在第二放大器中用作相邻差分级的虚拟晶体管
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8.发明授权Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators 有权用于消除比较器的输入电容的有源负电容电路的方法和装置公开(公告)号：US09264056B2
公开(公告)日：2016-02-16
申请号：US14672214
申请日：2015-03-29
Applicant: Tensorcom, Inc.
Inventor： Dai Dai
CPC classification number: H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.
Abstract translation: 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 该取消扩展了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS组成，其中电容器连接其源极，其中每个NMOS由电流源偏置。
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9.发明申请Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators 有权用于消除比较器的输入电容的有源负电容电路的方法和装置公开(公告)号：US20160134293A1
公开(公告)日：2016-05-12
申请号：US14995471
申请日：2016-01-14
Applicant: Tensorcom, Inc.
Inventor： Dai Dai
CPC classification number: H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
Abstract: A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal.
Abstract translation: 负电容电路包括耦合到第一晶体管的漏极和第二晶体管的栅极的第一节点; 耦合到所述第二晶体管的漏极和所述第一晶体管的栅极的第二节点; 耦合在所述第一晶体管的源极和所述第二晶体管的源极之间的电容器; 耦合在电源电压和第一晶体管的源极之间的第一电流镜; 以及耦合在电源电压和第二晶体管的源极之间的第二电流镜。 该电路可被配置为在较短时间段内驱动第一和第二节点之间的差分电容性负载，从而增加差分信号的传输带宽。
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