公开(公告)号：US5825710A

公开(公告)日：1998-10-20

申请号：US806828

申请日：1997-02-26

申请人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

发明人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks. The dedicated precharge signal and a succeeding activate signal for activating a different memory block are overlapped in timing so that the precharge sequence is implanted in the succeeding activate signal and the data access time is shortened.

公开(公告)号：US5936903A

公开(公告)日：1999-08-10

申请号：US130652

申请日：1998-08-07

申请人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

发明人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks. The dedicated precharge signal and a succeeding activate signal for activating a different memory block are overlapped in timing so that the precharge sequence is implanted in the succeeding activate signal and the data access time is shortened.

公开(公告)号：US5995438A

公开(公告)日：1999-11-30

申请号：US130664

申请日：1998-08-07

申请人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

发明人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks. The dedicated precharge signal and a succeeding activate signal for activating a different memory block are overlapped in timing so that the precharge sequence is implanted in the succeeding activate signal and the data access time is shortened.

摘要翻译： 一种能够对每个存储体进行段预充电的同步动态RAM。 在该SDRAM中，每个存储体被分成多个存储块。 这些存储器块中的每一个在内部具有自己的行存取电路，但是执行独立的预充电操作。 对存储体的访问可以在外部进行协调，并且可以将预充电操作分别应用于这些存储器块，同时允许使用其他块上可用的行缓存。 SDRAM还包括控制装置，用于根据每个存储体的预充电信号向每个存储块生成专用预充电信号。 每个专用预充电信号独立地对相应的存储器块进行预充电，而与其它存储器块执行的访问操作无关。 用于激活不同存储器块的专用预充电信号和后续激活信号在定时中重叠，使得预充电序列被植入到后续激活信号中，并且数据访问时间缩短。