公开(公告)号：US5801580A

公开(公告)日：1998-09-01

申请号：US756792

申请日：1996-11-26

申请人： Chuan-Yu Wu

发明人： Chuan-Yu Wu

IPC分类号： G05F3/24 ,  G05F3/26 ,  G05F1/10

CPC分类号： G05F3/262 ,  G05F3/247

摘要： A self-biased voltage-regulated current source is disclosed. The present invention includes a current source circuit for generating a constant output current; a voltage source for supplying an unstable voltage for the current source circuit; a regulating circuit for generating a regulated voltage coupled to the current source circuit; and a bias circuit, coupled to the regulating circuit, for generating a bias current to the regulating circuit and the current source circuit, where the bias current is greater than the output current of the current source circuit.

摘要翻译： 公开了一种自偏压电压调节电流源。 本发明包括用于产生恒定输出电流的电流源电路; 用于为电流源电路提供不稳定电压的电压源; 用于产生耦合到所述电流源电路的调节电压的调节电路; 以及耦合到所述调节电路的偏置电路，用于向所述调节电路和所述电流源电路产生偏置电流，其中所述偏置电流大于所述电流源电路的输出电流。

公开(公告)号：US5936903A

公开(公告)日：1999-08-10

申请号：US130652

申请日：1998-08-07

申请人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

发明人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks. The dedicated precharge signal and a succeeding activate signal for activating a different memory block are overlapped in timing so that the precharge sequence is implanted in the succeeding activate signal and the data access time is shortened.

公开(公告)号：US07043598B2

公开(公告)日：2006-05-09

申请号：US10036838

申请日：2001-12-31

申请人： Chuan-Yu Wu ,  Jia-Ming Yang ,  Chris Huang

发明人： Chuan-Yu Wu ,  Jia-Ming Yang ,  Chris Huang

IPC分类号： G11C8/18

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618

摘要： In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second possible “refresh blocks”. If its memory block does not contend with the current first possible refresh block, an externally generated access to one of the N memory blocks is permitted and at least a portion of the refresh block is refreshed during a certain interval. In another aspect, the externally generated access is permitted and at least a portion of the current second possible refresh block is refreshed during the same certain interval if: i) the memory block of the externally generated access contends with the current first possible refresh block and ii) the current first and second possible refresh blocks are different ones of the N memory blocks.

公开(公告)号：US5825710A

公开(公告)日：1998-10-20

申请号：US806828

申请日：1997-02-26

申请人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

发明人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks. The dedicated precharge signal and a succeeding activate signal for activating a different memory block are overlapped in timing so that the precharge sequence is implanted in the succeeding activate signal and the data access time is shortened.

公开(公告)号：US20050171910A1

公开(公告)日：2005-08-04

申请号：US10768042

申请日：2004-02-02

申请人： Chuan-Yu Wu ,  Chao-Hung Wang ,  Sung-Ping Cheng ,  Der-Lind Duh ,  Chii-Yah Yuan ,  Jen-Yau Kuo

发明人： Chuan-Yu Wu ,  Chao-Hung Wang ,  Sung-Ping Cheng ,  Der-Lind Duh ,  Chii-Yah Yuan ,  Jen-Yau Kuo

IPC分类号： G06Q10/00 ,  G06F17/60

CPC分类号： G06Q10/06

摘要： A method for integrating enterprise collaborative operations in the product lifecycle management (PLM) and a system thereof are proposed. The system comprises at least a message server, at least a web server, a system engineering service platform server, at least a PLM application system server and an enterprise portal server. The system can build a system integration environment between customers, central manufacturers, and providers and offer a collaborative platform between enterprises. Information can thus be interchanged in real time in this system integration environment in the whole PLM from idea through specification requirement, design, development, manufacturing to termination, thereby providing a system integration method and environment for collaborative management, development, manufacturing and marketing between enterprises, providers and customers.

摘要翻译： 提出了一种将产品生命周期管理（PLM）及其系统中的企业协作运营整合的方法。 系统至少包括消息服务器，至少web服务器，系统工程服务平台服务器，至少PLM应用系统服务器和企业门户服务器。 该系统可以在客户，中央制造商和供应商之间建立系统集成环境，并提供企业之间的协作平台。 因此，信息可以在整个PLM的系统集成环境中实时互换，从思想到规范要求，设计，开发，制造到终止，从而为企业之间的协同管理，开发，制造和营销提供系统集成方法和环境 ，提供商和客户。

公开(公告)号：US07443282B2

公开(公告)日：2008-10-28

申请号：US11122054

申请日：2005-05-05

申请人： Mengru Tu ,  Kuo-Sue Lo ,  Chuan-Yu Wu ,  Cheng-Wei Huang ,  Ho-Chun Lei

发明人： Mengru Tu ,  Kuo-Sue Lo ,  Chuan-Yu Wu ,  Cheng-Wei Huang ,  Ho-Chun Lei

IPC分类号： H04Q5/22 ,  G08B13/14

CPC分类号： G06Q10/06

摘要： A system and method, including software and hardware, for providing an accurate, real-time, and synchronized view of supply chain information. The system utilizes various RFID technologies (like an RFID tag, an RFID reader, and an RFID middleware software) to collect and manage data in real time. It then implements a synchronization mechanism to synchronize supply chain data from various data sources within and across a company in near real time fashion to allow different types of enterprise users, both internal and external, to access the synchronized information and take synchronized action within an appropriate timeframe.

摘要翻译： 一种包括软件和硬件的系统和方法，用于提供准确，实时和同步的供应链信息视图。 该系统利用各种RFID技术（如RFID标签，RFID读取器和RFID中间件软件）实时收集和管理数据。 然后，它实现一种同步机制，可以以几乎实时的方式在公司内部和跨公司的各种数据源同步供应链数据，以允许不同类型的内部和外部企业用户访问同步信息，并在适当的情况下采取同步行动 大体时间。

公开(公告)号：US20060250248A1

公开(公告)日：2006-11-09

申请号：US11122054

申请日：2005-05-05

申请人： Mengru Tu ,  Kuo-Sue Lo ,  Chuan-Yu Wu ,  Cheng-Wei Huang ,  Ho-Chun Lei

发明人： Mengru Tu ,  Kuo-Sue Lo ,  Chuan-Yu Wu ,  Cheng-Wei Huang ,  Ho-Chun Lei

IPC分类号： G08B13/14

CPC分类号： G06Q10/06

摘要： A system and method, including software and hardware, for providing an accurate, real-time, and synchronized view of supply chain information. The system utilizes various RFID technologies (like an RFID tag, an RFID reader, and an RFID middleware software) to collect and manage data in real time. It then implements a synchronization mechanism to synchronize supply chain data from various data sources within and across a company in near real time fashion to allow different types of enterprise users, both internal and external, to access the synchronized information and take synchronized action within an appropriate timeframe.

摘要翻译： 一种包括软件和硬件的系统和方法，用于提供准确，实时和同步的供应链信息视图。 该系统利用各种RFID技术（如RFID标签，RFID读取器和RFID中间件软件）实时收集和管理数据。 然后，它实现一种同步机制，可以以几乎实时的方式在公司内部和跨公司的各种数据源同步供应链数据，以允许内部和外部的不同类型的企业用户访问同步的信息，并在适当的情况下采取同步的操作 大体时间。

公开(公告)号：US5995438A

公开(公告)日：1999-11-30

申请号：US130664

申请日：1998-08-07

申请人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

发明人： Terry Jeng ,  Chuan-Yu Wu ,  Jason Hou

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks. The dedicated precharge signal and a succeeding activate signal for activating a different memory block are overlapped in timing so that the precharge sequence is implanted in the succeeding activate signal and the data access time is shortened.

摘要翻译： 一种能够对每个存储体进行段预充电的同步动态RAM。 在该SDRAM中，每个存储体被分成多个存储块。 这些存储器块中的每一个在内部具有自己的行存取电路，但是执行独立的预充电操作。 对存储体的访问可以在外部进行协调，并且可以将预充电操作分别应用于这些存储器块，同时允许使用其他块上可用的行缓存。 SDRAM还包括控制装置，用于根据每个存储体的预充电信号向每个存储块生成专用预充电信号。 每个专用预充电信号独立地对相应的存储器块进行预充电，而与其它存储器块执行的访问操作无关。 用于激活不同存储器块的专用预充电信号和后续激活信号在定时中重叠，使得预充电序列被植入到后续激活信号中，并且数据访问时间缩短。

公开(公告)号：US5805010A

公开(公告)日：1998-09-08

申请号：US759783

申请日：1996-12-03

申请人： Chuan-Yu Wu

发明人： Chuan-Yu Wu

IPC分类号： G05F3/26 ,  G05F1/10

CPC分类号： G05F3/262

摘要： A low-current source circuit for generating a constant current and a reference voltage from a fluctuating voltage source is disclosed. A resistive circuit is electrically connected to the voltage source for determining amount of the constant current. A charging circuit is electrically connected to a second lead of the resistive circuit and the voltage source for supporting a charging path for the voltage source. A current output circuit is electrically connected to the second lead of the resistive circuit for outputting the constant current. A stabilizing circuit is electrically connected between the second lead of the resistive circuit and a control lead of the current output circuit for stabilizing the current output circuit. A reference voltage circuit is electrically connected to an output lead and the control lead of the current output circuit for generating the reference voltage.

摘要翻译： 公开了一种用于从波动电压源产生恒定电流和参考电压的低电流源电路。 电阻电路电连接到电压源以确定恒定电流的量。 充电电路电连接到电阻电路的第二引线和用于支撑用于电压源的充电路径的电压源。 电流输出电路电连接到电阻电路的第二引线以输出恒定电流。 稳定电路电连接在电阻电路的第二引线和电流输出电路的控制引线之间，用于稳定电流输出电路。 参考电压电路电连接到输出引线和电流输出电路的控制引线以产生参考电压。