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公开(公告)号：US20050238115A1
公开(公告)日：2005-10-27
申请号：US11115112
申请日：2005-04-27
申请人： Teruaki Hasegawa , Takaaki Konishi
发明人： Teruaki Hasegawa , Takaaki Konishi
CPC分类号： H04L27/362
摘要： A first interpolation section 14 and a second interpolation section 24 perform sampling on input data Id4 and Qd4 having a sampling frequency fover so that resulting data will have a sampling frequency fsamp, which is equal to an operating clock frequency of a digital-to-analog converter, which is an output destination. In the above manner, the data is interpolated. At this time, the first interpolation section 14 and the second interpolation section 24 perform interpolation using a frequency ratio between the sampling frequency fover and the sampling frequency fsamp. Then,output data Id5 and Qd5 having the sampling frequency fsamp is outputted to a quadrature modulation section 31.
摘要翻译： 第一内插部分14和第二内插部分24对具有采样频率fover的输入数据Id 4和Qd 4执行采样，使得所得到的数据将具有采样频率fsamp，该采样频率fsamp等于数字到 -analog转换器，它是一个输出目标。 以上述方式，内插数据。 此时，第一内插部14和第二内插部24使用采样频率fover和采样频率fsamp之间的频率比进行插值。 然后，具有采样频率fsamp的输出数据Id 5和Qd 5输出到正交调制部分31。
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公开(公告)号：US07450660B2
公开(公告)日：2008-11-11
申请号：US11115112
申请日：2005-04-27
申请人： Teruaki Hasegawa , Takaaki Konishi
发明人： Teruaki Hasegawa , Takaaki Konishi
IPC分类号： H04L27/36
CPC分类号： H04L27/362
摘要： A first interpolation section 14 and a second interpolation section 24 perform sampling on input data Id4 and Qd4 having a sampling frequency fover so that resulting data will have a sampling frequency fsamp, which is equal to an operating clock frequency of a digital-to-analog converter, which is an output destination. In the above manner, the data is interpolated. At this time, the first interpolation section 14 and the second interpolation section 24 perform interpolation using a frequency ratio between the sampling frequency fover and the sampling frequency fsamp. Then, output data Id5 and Qd5 having the sampling frequency fsamp is outputted to a quadrature modulation section 31.
摘要翻译： 第一内插部分14和第二内插部分24对具有采样频率fover的输入数据Id 4和Qd 4执行采样，使得所得到的数据将具有采样频率fsamp，该采样频率fsamp等于数字到 -analog转换器，它是一个输出目标。 以上述方式，内插数据。 此时，第一内插部14和第二内插部24使用采样频率fover和采样频率fsamp之间的频率比进行插值。 然后，具有采样频率fsamp的输出数据Id 5和Qd 5输出到正交调制部分31。
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公开(公告)号：US07277502B2
公开(公告)日：2007-10-02
申请号：US10505926
申请日：2003-03-10
IPC分类号： H04L27/00
CPC分类号： H04L27/3872 , H04L2027/0067
摘要： A carrier recovery apparatus capable of detecting a phase error of modulation signal by a simple calculation, reducing the circuit scale, and improving the frequency capture characteristic and phase jitter characteristic is presented. This carrier recovery apparatus comprises a symbol estimating unit for estimating the transmitted symbol, a phase error detector for generating a normalized phase error signal on the basis of the estimated symbol and reception signal, a loop filter for filtering the phase error, and a numerical control oscillator controlled by the loop filter.
摘要翻译： 提出了能够通过简单的计算来检测调制信号的相位误差，减小电路规模，提高频率捕获特性和相位抖动特性的载波恢复装置。 该载波恢复装置包括用于估计发射符号的符号估计单元，用于基于估计的符号和接收信号产生归一化相位误差信号的相位误差检测器，用于滤波相位误差的环路滤波器和数字控制 振荡器由环路滤波器控制。
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公开(公告)号：US20050207514A1
公开(公告)日：2005-09-22
申请号：US10505926
申请日：2003-03-10
CPC分类号： H04L27/3872 , H04L2027/0067
摘要： A carrier recovery apparatus capable of detecting a phase error of modulation signal by a simple calculation, reducing the circuit scale, and improving the frequency capture characteristic and phase jitter characteristic is presented. This carrier recovery apparatus comprises a symbol estimating unit for estimating the transmitted symbol, a phase error detecting means for generating a normalized phase error signal on the basis of the estimated symbol and reception signal, a loop filter for filtering the phase error, and a numerical control oscillator controlled by the loop filter.
摘要翻译： 提出了能够通过简单的计算来检测调制信号的相位误差，减小电路规模，提高频率捕获特性和相位抖动特性的载波恢复装置。 该载波恢复装置包括用于估计发射符号的符号估计单元，用于基于估计的符号和接收信号产生归一化相位误差信号的相位误差检测装置，用于滤波相位误差的环路滤波器，以及数字 控制振荡器由环路滤波器控制。
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公开(公告)号：US6075829A
公开(公告)日：2000-06-13
申请号：US865829
申请日：1997-05-30
CPC分类号： H04H40/18 , H03B5/1203 , H03B5/1231 , H03B5/1243 , H03D3/007 , H03J1/005 , H03L7/18
摘要： A digital broadcast receiver for receiving a digital modulation signal of the present invention includes channel selection means inputting a digital modulation signal of a radio frequency band and frequency converting a desired digital modulation signal into a designated intermediate frequency signal; oscillation means for generating a local oscillation signal used for frequency conversion at the channel selection means; oscillation frequency control means for controlling a frequency of the local oscillation signal at the oscillation means; phase noise characteristic control means for improving a phase noise characteristic of the local oscillation signal generated at the oscillation means; filter means for extracting the intermediate frequency signal selected at channel selection means; orthogonal detection means for orthogonally detecting the intermediate frequency signal extracted at the filter means; A/D converter means for converting the analog output of the orthogonal detection means into a digital signal; and digital demodulation means for digitally demodulating the output of the A/D converter means; and makes a high performance digital reception possible which can improve an AFC function by the channel selection means and can improve a bit error rate at the same time.
摘要翻译： 用于接收本发明的数字调制信号的数字广播接收机包括：信道选择装置，输入无线电频带的数字调制信号，并将期望的数字调制信号频率转换成指定的中频信号; 用于在频道选择装置处产生用于频率转换的本地振荡信号的振荡装置; 振荡频率控制装置，用于控制振荡装置处的本地振荡信号的频率; 相位噪声特性控制装置，用于改善在振荡装置产生的本地振荡信号的相位噪声特性; 滤波器装置，用于提取在频道选择装置处选择的中频信号; 正交检测装置，用于正交检测在滤波装置处提取的中频信号; A / D转换装置，用于将正交检测装置的模拟输出转换成数字信号; 以及数字解调装置，用于数字解调A / D转换装置的输出; 并且可以实现高性能数字接收，这可以通过信道选择装置改善AFC功能，并且可以同时提高误码率。
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公开(公告)号：US07333576B2
公开(公告)日：2008-02-19
申请号：US10342218
申请日：2003-01-15
申请人： Toshiyuki Satomi , Naoya Tokunaga , Takaaki Konishi , Hisaya Kato
发明人： Toshiyuki Satomi , Naoya Tokunaga , Takaaki Konishi , Hisaya Kato
CPC分类号： H04N5/455 , H04L7/06 , H04N5/211 , H04N5/4401 , H04N21/4382
摘要： A synchronization error occurs when a DTV signal is distorted on a transmission path and this deteriorates demodulation capability. The digital demodulation device and the synchronization detecting method of the invention can correct the synchronization position when determining that a synchronization error has occurred. A controller receives a center tap coefficient, for example, from a waveform equalizer and compares the coefficient with a given center tap coefficient threshold. If the coefficient is smaller than the threshold, the controller determines that a synchronization detector has made a synchronization error and outputs a control signal. The synchronization detector receiving the control signal re-detects a sync signal included in a received signal, to detect a new correct sync signal and thus correct the synchronization error.
摘要翻译： 当DTV信号在传输路径上失真时，发生同步错误，并且这会降低解调能力。 本发明的数字解调装置和同步检测方法可以在确定发生同步错误时校正同步位置。 控制器例如从波形均衡器接收中心抽头系数，并将系数与给定中心抽头系数阈值进行比较。 如果系数小于阈值，则控制器确定同步检测器已经做出同步误差并输出控制信号。 接收控制信号的同步检测器重新检测包含在接收信号中的同步信号，以检测新的正确同步信号，从而校正同步误差。
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公开(公告)号：US6072999A
公开(公告)日：2000-06-06
申请号：US829978
申请日：1997-04-01
CPC分类号： H01P1/20336
摘要： A receiving apparatus is presented, in which a channel frequency can be selected over a wide band with an increased attenuation at an image frequency and/or at a local oscillation frequency by including a tunable filter having a following construction. Microstrip lines are connected between either one of the input or the output terminal or both of the input and output terminals of the tunable filter; a plurality of resonant circuits are formed by each of a plurality of coils and a plurality of variable capacitance diodes; and the coils are electromagnetically coupled and where a voltage applied to each cathode of each of a plurality of variable capacitance diodes through each of a plurality of resistors is controlled to tune a frequency to be received.
摘要翻译： 提出了一种接收装置，其中可以通过包括具有以下结构的可调谐滤波器在宽频带上选择具有在图像频率和/或本地振荡频率处的增加的衰减的信道频率。 微带线连接在可调谐滤波器的输入或输出端子之一或输入和输出端子之间; 由多个线圈和多个可变电容二极管中的每一个形成多个谐振电路; 并且线圈被电磁耦合，并且其中通过多个电阻器中的每一个施加到多个可变电容二极管中的每一个的每个阴极的电压被控制以调谐待接收的频率。
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公开(公告)号：US07133481B2
公开(公告)日：2006-11-07
申请号：US10311638
申请日：2002-04-05
申请人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Kazuaki Suzuki , Kazuya Ueda
发明人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Kazuaki Suzuki , Kazuya Ueda
IPC分类号： H04L7/00
摘要： An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication section 111 multiplies a clock CK. A switchable sampling section 112 selects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling section 112 switches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.
摘要翻译： 输入信号DT包含符合ATSC标准的片段同步信号。 时钟倍增部分111将时钟CK相乘。 可切换取样部112从由倍增时钟定义的多个定时点中选择采样点，并对选择的采样点对输入信号DT进行采样。 此外，可切换采样部112在同步未建立状态下将采样点从一个切换到另一个。 一旦段同步建立，同步检测装置可以保持同步建立状态，直到现场同步检测失败，或者同步检测装置可以在基于位错误率RT在时间方向上移动同步检测信号之后输出同步检测信号 的输入信号。
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公开(公告)号：US06671002B1
公开(公告)日：2003-12-30
申请号：US09555150
申请日：2000-08-07
申请人： Takaaki Konishi , Kazuya Ueda , Hiroshi Azakami
发明人： Takaaki Konishi , Kazuya Ueda , Hiroshi Azakami
IPC分类号： H04N544
CPC分类号： H04N5/4401 , H03G3/3052 , H03G3/3078 , H03L7/107 , H04L27/08 , H04N5/211 , H04N5/52
摘要： The loop gain of an AGC circuit 7 and the loop gain of a clock regenerating circuit 6 are increased (the gain of an amplifier is increased, or the band of a loop filter is widened) until a synchronizing signal (a segment synchronizing signal or a field synchronizing signal) is detected. The loop gain of the AGC circuit 7 and the loop gain of the clock regenerating circuit 6 are decreased (the gain of the amplifier is decreased, or the band of the loop filter is narrowed) after the synchronizing signal is detected. Consequently, it is possible to make a reduction of a time period required until convergence processing is completed in the AGC circuit and the clock regenerating circuit compatible with an improvement of a ghost disturbance removal performance and accurate clock regeneration.
摘要翻译： AGC电路7的环路增益和时钟再生电路6的环路增益增加（放大器的增益增加或环路滤波器的频带被加宽），直到同步信号（段同步信号或 场同步信号）。 在检测到同步信号之后，AGC电路7的环路增益和时钟再生电路6的环路增益被减小（放大器的增益减小或环路滤波器的频带变窄）。因此， 可以减少在AGC电路和时钟再生电路中的会聚处理完成所需的时间段，其与改善重影干扰去除性能和精确的时钟再生相兼容。
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公开(公告)号：US07302021B2
公开(公告)日：2007-11-27
申请号：US09878427
申请日：2001-06-12
申请人： Takaaki Konishi , Hiroshi Azakami , Kazuya Ueda , Naoya Tokunaga
发明人： Takaaki Konishi , Hiroshi Azakami , Kazuya Ueda , Naoya Tokunaga
IPC分类号： H04L27/08
CPC分类号： H04N5/4446 , H03G3/3068 , H03G3/3089 , H04H40/18 , H04N5/4401 , H04N5/50 , H04N5/52 , H04N21/42607
摘要： In a digital broadcast receiving apparatus for amplifying a received modulated digital signal wave with automatically adjusted gain and demodulating the modulated signal wave to a digital signal, a tuner frequency-converts the modulated digital signal wave to generate a first modulated signal. A first automatic gain control amplification unit controls gain of the tuner to make a level of the first modulated signal at a first predetermined level. An A/D converter converts the first modulated signal into a second modulated signal. A demodulator demodulates the second modulated signal to generate a first demodulated digital signal. A second automatic gain control amplifier generates a second demodulated digital signal where frequency fluctuations included in the digital modulated wave are eliminated.
摘要翻译： 在一种数字广播接收装置中，用于利用自动调节增益放大接收到的调制数字信号波并将调制信号波解调为数字信号，调谐器对调制数字信号波进行频率转换以产生第一调制信号。 第一自动增益控制放大单元控制调谐器的增益使第一调制信号的电平达到第一预定电平。 A / D转换器将第一调制信号转换成第二调制信号。 解调器解调第二调制信号以产生第一解调数字信号。 第二自动增益控制放大器产生第二解调数字信号，其中消除了数字调制波中包括的频率波动。
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