公开(公告)号：US11670386B2

公开(公告)日：2023-06-06

申请号：US16734517

申请日：2020-01-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Stephen K. Heinrich-Barna ,  Clyde F. Dunn ,  Aswin N. Mehta ,  John H. MacPeak

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0425 ,  G11C16/10

Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

公开(公告)号：US10535409B2

公开(公告)日：2020-01-14

申请号：US15394095

申请日：2016-12-29

Applicant: Texas Instruments Incorporated

Inventor： Stephen K. Heinrich-Barna ,  Clyde F. Dunn ,  Aswin N. Mehta ,  John H. Macpeak

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.