公开(公告)号：US20240213998A1

公开(公告)日：2024-06-27

申请号：US18129604

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Rajashekar Goroju ,  Prasanth K ,  Dileepkumar Ramesh Bhat ,  Rakul Viswanath ,  Sravana Kumar Goli ,  Rahul Sharma

IPC: H03M1/38

CPC classification number: H03M1/38

Abstract: An example apparatus includes: controller circuitry configured to: provide switch signals to capacitive digital to analog converter (C-DAC) circuitry, the C-DAC circuitry including switches; configuring the switches into a third configuration begin an Auto Zero (AZ) phase with a third switch in a closed state; configuring the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to a first configuration; configuring the switches into a fifth configuration to repeat the transition of a first switch and a second switch to the open state corresponding to a second configuration; configuring the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to a second configuration; and performing an AZ decision with the switches in the sixth configuration.

公开(公告)号：US12261620B2

公开(公告)日：2025-03-25

申请号：US18129604

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Rajashekar Goroju ,  Prasanth K ,  Dileepkumar Ramesh Bhat ,  Rakul Viswanath ,  Sravana Kumar Goli ,  Rahul Sharma

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/08 ,  H03M1/16 ,  H03M1/46 ,  H03M1/80

Abstract: An example apparatus includes: controller circuitry configured to: provide switch signals to capacitive digital to analog converter (C-DAC) circuitry, the C-DAC circuitry including switches; configuring the switches into a third configuration begin an Auto Zero (AZ) phase with a third switch in a closed state; configuring the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to a first configuration; configuring the switches into a fifth configuration to repeat the transition of a first switch and a second switch to the open state corresponding to a second configuration; configuring the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to a second configuration; and performing an AZ decision with the switches in the sixth configuration.

公开(公告)号：US20240106450A1

公开(公告)日：2024-03-28

申请号：US18090997

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Rajashekar Goroju ,  Prasanth K ,  Dileepkumar Ramesh Bhat ,  Rahul Sharma

IPC: H03M1/12

CPC classification number: H03M1/1245

Abstract: An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.