公开(公告)号：US20210208657A1

公开(公告)日：2021-07-08

申请号：US17139249

申请日：2020-12-31

申请人： Texas Instruments Incorporated

发明人： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC分类号： G06F1/3203 ,  G06F11/36

摘要： An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

公开(公告)号：US20240077925A1

公开(公告)日：2024-03-07

申请号：US18505037

申请日：2023-11-08

申请人： Texas Instruments Incorporated

发明人： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC分类号： G06F1/3203 ,  G06F11/36

CPC分类号： G06F1/3203 ,  G06F11/3656

摘要： Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.