Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing
    1.
    发明申请
    Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing 审中-公开
    使用ALD和高温短时退火的超短发射体形成

    公开(公告)号:US20140339678A1

    公开(公告)日:2014-11-20

    申请号:US14450857

    申请日:2014-08-04

    Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.

    Abstract translation: 一种包含双极晶体管的集成电路,其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域,以及在基极层中小于40纳米深的发射极 - 基极结。 一种形成双极晶体管的工艺,其包括在基极层和发射极层之间形成发射极掺杂剂原子层,随后进行闪光或激光退火步骤,以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

    BIPOLAR TRANSISTOR IN BIPOLAR-CMOS TECHNOLOGY

    公开(公告)号:US20130328130A1

    公开(公告)日:2013-12-12

    申请号:US13967918

    申请日:2013-08-15

    Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

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