公开(公告)号：US08470644B2

公开(公告)日：2013-06-25

申请号：US13646199

申请日：2012-10-05

Applicant: Texas Instruments Incorporated

Inventor： Frank Yu ,  Lance C. Wright ,  Chien Te Feng ,  Sandra J. Horton

IPC: H01L21/00

CPC classification number: H01L23/4951 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/30519 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/1305 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB.

Abstract translation: 形成电子组件的方法包括将半导体管芯的底部的背面金属层附着。 背面金属层的区域与模具的底部区域相匹配。 芯片焊盘和引线封装在模制材料内。 引线包括包括接合部分的暴露部分。 间隙沿着包装的底部表面暴露背面金属层。 接合线将管芯顶部的焊盘连接到引线和接合部分。 封装半导体器件焊接到印刷电路板（PCB）。 背面金属层和引线的接合部分是焊接在所述PCB上的衬底焊盘。