公开(公告)号：US12235319B2

公开(公告)日：2025-02-25

申请号：US18520797

申请日：2023-11-28

Applicant: Texas Instruments Incorporated

Inventor： Abhinay Patil ,  Kavitha Balaramaiah ,  Mahadev Gopalakrishnan

IPC: G01R31/3177 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/327 ,  G06F13/16

Abstract: Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.

公开(公告)号：US20250164554A1

公开(公告)日：2025-05-22

申请号：US19024722

申请日：2025-01-16

Applicant: Texas Instruments Incorporated

Inventor： Abhinay Patil ,  Kavitha Balaramaiah ,  Mahadev Gopalakrishnan

IPC: G01R31/3177 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/327 ,  G06F13/16

Abstract: Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.

公开(公告)号：US20240393392A1

公开(公告)日：2024-11-28

申请号：US18520797

申请日：2023-11-28

Applicant: Texas Instruments Incorporated

Inventor： Abhinay Patil ,  Kavitha Balaramaiah ,  Mahadev Gopalakrishnan

IPC: G01R31/3177 ,  G06F13/16

Abstract: Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.