-
1.发明授权Enhanced resolution successive-approximation register analog-to-digital converter and method 有权增强分辨率逐次逼近寄存器模数转换器和方法公开(公告)号：US09252800B1
公开(公告)日：2016-02-02
申请号：US14462916
申请日：2014-08-19
Applicant: Texas Instruments Incorporated
Inventor： Joonsung Park , Krishnaswamy Nagaraj , Mikel Ash
Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.
Abstract translation: 提供了增强分辨率逐次逼近寄存器（SAR）模数转换器（ADC），其包括数模转换器（DAC），比较器和增强分辨率SAR控制逻辑。 DAC包括配置为将M位数字输入转换为模拟输出的模拟电路。 比较器包括多个耦合电容器。 增强分辨率SAR控制逻辑被配置为产生输入电压的M位近似值，并将剩余电压存储在至少一个耦合电容器中。 残余电压表示输入电压和输入电压的M位近似之间的差。 增强分辨率SAR控制逻辑还被配置为基于存储的残留电压来产生输入电压的N位近似，其中N> M。
-
2.发明申请ENHANCED RESOLUTION SUCCESSIVE-APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD 有权增强分辨率随机逼近寄存器模拟数字转换器和方法公开(公告)号：US20160056831A1
公开(公告)日：2016-02-25
申请号：US14462916
申请日：2014-08-19
Applicant: Texas Instruments Incorporated
Inventor： Joonsung Park , Krishnaswamy Nagaraj , Mikel Ash
Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.
Abstract translation: 提供了增强分辨率逐次逼近寄存器（SAR）模数转换器（ADC），其包括数模转换器（DAC），比较器和增强分辨率SAR控制逻辑。 DAC包括配置为将M位数字输入转换为模拟输出的模拟电路。 比较器包括多个耦合电容器。 增强分辨率SAR控制逻辑被配置为产生输入电压的M位近似值，并将剩余电压存储在至少一个耦合电容器中。 残余电压表示输入电压和输入电压的M位近似之间的差。 增强分辨率SAR控制逻辑还被配置为基于存储的残留电压来产生输入电压的N位近似，其中N> M。
-
Search Results
2
records
(took 0.011 seconds)
