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    DIGITALLY ENHANCED DIGITAL-TO-ANALOG CONVERTER RESOLUTION
    1.
    发明公开
    DIGITALLY ENHANCED DIGITAL-TO-ANALOG CONVERTER RESOLUTION 审中-公开

    公开(公告)号：US20230412187A1

    公开(公告)日：2023-12-21

    申请号：US18031188

    申请日：2021-10-29

    Applicant: Ciena Corporation

    Inventor： Mohammad Honarparvar ,  Sadok Aouini ,  Jerry Yee-Tung Lam ,  Soheyl Ziabakhsh Shalmani ,  Naim Ben-Hamida

    IPC: H03M1/66 ,  H03M1/20 ,  H03M1/06

    CPC classification number: H03M1/661 ,  H03M1/0607 ,  H03M1/0682 ,  H03M1/20

    Abstract: Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

    ANALOG-TO-INFORMATION CONVERSION USING ANALOG PRE-PROCESSING SENSING OF MULTI-BAND SIGNALS
    2.
    发明公开
    ANALOG-TO-INFORMATION CONVERSION USING ANALOG PRE-PROCESSING SENSING OF MULTI-BAND SIGNALS 审中-公开

    公开(公告)号：US20230387935A1

    公开(公告)日：2023-11-30

    申请号：US18203597

    申请日：2023-05-30

    Applicant: Alphacore, Inc.

    Inventor： Phaneendra Bikkina ,  Esko Mikkola

    IPC: H03M1/20 ,  H03M1/12

    CPC classification number: H03M1/20 ,  H03M1/1245 ,  H03M1/1205

    Abstract: Analog-to-information converter and method for performing analog-to-information conversion samples and down-converts N samples of an input multi-band signal using M analog sampling filters or samplers, where N is less than M. The N samples of the input multi-band signal are digitized to produce N digital samples of the input multi-band signal, which are multiplexed into M digital samples of the input multi-band signal. The M digital samples are up-converted and filtered at M digital reconstruction filters to produce a digital multi-band signal, which is processed at a processing unit to obtain information contained in the digital multi-band signal.

    CAPACITIVE SENSING SYSTEM AND METHOD
    5.
    发明申请
    CAPACITIVE SENSING SYSTEM AND METHOD 有权
    电容式感应系统及方法

    公开(公告)号：US20160156366A1

    公开(公告)日：2016-06-02

    申请号：US14897854

    申请日：2014-06-11

    Applicant: IEE INTERNATIONAL ELECTRONICS & ENGINEERING S.A.

    Inventor： Laurent LAMESCH

    IPC: H03M1/20 ,  H03M1/12 ,  H03C3/02

    CPC classification number: H03M1/20 ,  H03C3/02 ,  H03M1/124 ,  H03M1/201

    Abstract: A capacitive sensing system operates according to a method which uses an ADC with a low resolution r, to produce a digital signal with a higher resolution R. The analog signal to be digitized is modulated with a triangular or saw-tooth modulating signal, so that a modulated analog signal is obtained, which is sampled with the ADC. Thereby, digital samples are produced. An average is taken over N (>1) successive digital samples. The triangular or saw-tooth signal is chosen to have a peak-to-peak amplitude corresponding at least approximately to an integer multiple L, with L≧1, of the quantization step size of the ADC. The saw-tooth or triangular signal, furthermore, has a number M, of periods per each sequence of N samples. M and N are chosen such that M>1 and M≠N and such that R=r*N/(k*gcd(N, M)*L), where gcd(M, N) is the greatest common divisor of N and M and where k=2 if the modulating signal is a saw-tooth signal and k=4 if the modulating signal is a triangular signal.

    Abstract translation: 电容式感测系统根据使用具有低分辨率r的ADC的方法进行工作，以产生具有更高分辨率R的数字信号。要被数字化的模拟信号用三角形或锯齿调制信号调制，使得 得到一个调制的模拟信号，用ADC进行采样。 从而产生数字样本。 N（> 1）个连续数字样本的平均数。 三角形或锯齿状信号被选择为具有至少近似于ADC的量化步长的L≥1的整数倍L的峰峰值幅度。 此外，锯齿或三角形信号具有每个N个样本的每个序列的周期数M。 M和N被选择为使得M> 1且M≠N，并且使得R = r * N /（k * gcd（N，M）* L），其中gcd（M，N）是N的最大公约数 如果调制信号是锯齿信号，则k = 2，如果调制信号是三角形信号，则k = 4。

    METHOD AND DEVICE FOR ANALOG/DIGITAL CONVERSION OF AN ANALOG SIGNAL
    6.
    发明申请
    METHOD AND DEVICE FOR ANALOG/DIGITAL CONVERSION OF AN ANALOG SIGNAL 有权
    用于模拟信号的模拟/数字转换的方法和装置

    公开(公告)号：US20160134297A1

    公开(公告)日：2016-05-12

    申请号：US14835980

    申请日：2015-08-26

    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

    Inventor： Laurent SIMONY

    IPC: H03M1/20 ,  H01L27/146 ,  H03M1/36 ,  H03M1/00 ,  H03M1/06

    CPC classification number: H03M1/20 ,  H01L27/14643 ,  H03M1/002 ,  H03M1/0604 ,  H03M1/188 ,  H03M1/36 ,  H03M1/56

    Abstract: A method includes a first analog/digital conversion of an analog signal over m bits, with m less than n, associated with a first full-scale value, and a second analog/digital conversion of the analog signal over m bits associated with a second full-scale value 2n-m times bigger than the first. The two analog/digital conversions are carried out simultaneously and respectively delivering a first intermediate digital word of m bits and a second intermediate digital word of m bits. The method also includes a digital post-processing carried out after the two analog/digital conversions and generating an n-bit digital word starting from at least one of the two intermediate digital words extended to n bits and from at least one threshold digital indication representative of at least one threshold lower than or equal to the first full-scale value.

    Abstract translation: 一种方法包括通过m比特的模拟信号的第一模拟/数字转换，具有与第一满量程值相关联的m小于n的模拟信号，以及在与第二满量程相关联的m位上的模拟信号的第二模拟/数字转换 全尺寸值比第一大2n-m倍。 两个模拟/数字转换同时执行，分别传送m位的第一中间数字字和m位的第二中间数字字。 该方法还包括在两个模拟/数字转换之后执行的数字后处理，并产生从扩展到n位的两个中间数字字中的至少一个开始的n位数字字，以及从至少一个阈值数字指示代表 的至少一个阈值小于或等于第一满量程值。

    Method and related device for generating a digital output signal corresponding to an analog input signal
    7.
    发明授权
    Method and related device for generating a digital output signal corresponding to an analog input signal 有权
    用于产生对应于模拟输入信号的数字输出信号的方法和相关装置

    公开(公告)号：US09071260B2

    公开(公告)日：2015-06-30

    申请号：US14447050

    申请日：2014-07-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mario Chiricosta ,  Calogero Marco Ippolito ,  Mario Maiore ,  Orlando Peluso ,  Michele Vaiana

    IPC: H03M1/20 ,  H03M1/06 ,  H03M1/12

    CPC classification number: H03M1/0626 ,  H03M1/0639 ,  H03M1/12 ,  H03M1/20

    Abstract: An embodiment of a circuit includes an input node, a generator, a combiner, a converter, and a filter. The input node is configured to receive an input signal in a first domain, and the generator is configured to generate a periodic signal in the first domain. The combiner is configured to combine the input and periodic signals into a resulting signal in the first domain, and the converter is configured to convert the resulting signal into a converted signal in a second domain. And the filter is configured to remove from the converted signal substantially all of a frequency component of the converted signal having substantially a same frequency as a frequency component of the periodic signal.

    Abstract translation: 电路的实施例包括输入节点，发生器，组合器，转换器和滤波器。 输入节点被配置为在第一域中接收输入信号，并且发生器被配置为在第一域中产生周期性信号。 组合器被配置为将输入和周期信号组合成第一域中的结果信号，并且转换器被配置为将结果信号转换为第二域中的转换信号。 并且滤波器被配置为从转换的信号中移除基本上所有的转换信号的频率分量具有与周期信号的频率分量基本相同的频率。

    ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD
    8.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD 有权
    模拟数字转换器和模拟数字转换方法

    公开(公告)号：US20150138007A1

    公开(公告)日：2015-05-21

    申请号：US14548886

    申请日：2014-11-20

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Kei SHIRAISHI ,  Junya MATSUNO ,  Masanori FURUTA

    IPC: H03M1/20 ,  H03M1/36 ,  H03M1/18 ,  H03M1/12

    CPC classification number: H03M1/20 ,  H03M1/0695 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/18 ,  H03M1/36 ,  H03M1/466 ,  H03M1/56 ,  H03M3/46

    Abstract: According to an embodiment, an analog-to-digital (AD) converter includes a first AD conversion unit, a selector and a second AD conversion unit. The first AD conversion unit performs AD conversion of an analog signal in a first period to generate an upper-bit digital signal. The selector selects not less than one reference voltage based on the upper-bit digital signal to obtain a selected reference voltage group in a voltage range narrower than a full scale. The second AD conversion unit performs AD conversion of the analog signal by using the selected reference voltage group. The first period starts before settling of the analog signal up to an accuracy corresponding to a total resolution of the first AD conversion unit and the second AD conversion unit.

    Abstract translation: 根据实施例，模数（AD）转换器包括第一AD转换单元，选择器和第二AD转换单元。 第一AD转换单元在第一周期中执行模拟信号的AD转换，以产生高位数字信号。 选择器基于高位数字信号选择不少于一个参考电压，以在比满量程更窄的电压范围内获得所选参考电压组。 第二AD转换单元通过使用所选择的参考电压组来执行模拟信号的AD转换。 第一时段在模拟信号稳定之前开始，直到对应于第一AD转换单元和第二AD转换单元的总分辨率的精度。

    A/D CONVERTER, SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM
    9.
    发明申请
    A/D CONVERTER, SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM 审中-公开
    A / D转换器，固态图像传感器和成像系统

    公开(公告)号：US20150129744A1

    公开(公告)日：2015-05-14

    申请号：US14520426

    申请日：2014-10-22

    Applicant: Canon Kabushiki Kaisha

    Inventor： Kazuhiro Sonoda ,  Shintaro Takenaka

    IPC: H03M1/34 ,  H03K3/037 ,  H03K3/64

    CPC classification number: H03K3/64 ,  H03M1/20 ,  H03M1/56

    Abstract: An A/D converter includes a comparator configured to compare an input voltage and a reference signal changing monotonically with respect to time and output a comparison result signal indicating a comparison result, a pulse signal generation circuit configured to generate a pulse signal in accordance with the comparison result signal, a counting unit configured to receive a first clock signal, and to count the first clock signal from a start of changing a level of the reference signal to when a level of the comparison result signal is changed, and a latch unit configured to latch the pulse signal at a timing which is defined by a plurality of clock signals including a second clock signal in phase with the first clock signal and a third clock signal having a different phase from that of the second clock signal.

    Abstract translation: A / D转换器包括：比较器，被配置为比较输入电压和参考信号相对于时间单调变化，并输出表示比较结果的比较结果信号;脉冲信号产生电路，被配置为根据 比较结果信号，被配置为接收第一时钟信号的计数单元，并且从开始将参考信号的电平改变到比较结果信号的电平改变时对第一时钟信号进行计数;以及闩锁单元配置 以由包括与第一时钟信号同相的第二时钟信号的多个时钟信号定义的定时和与第二时钟信号具有不同相位的第三时钟信号的定时锁存脉冲信号。

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