公开(公告)号：US20240028338A1

公开(公告)日：2024-01-25

申请号：US18479165

申请日：2023-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Rama VENKATASUBRAMANIAN ,  Dheera Balasubramanian SAMUDRALA ,  Alan DAVIS

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F9/38 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445

CPC classification number: G06F9/30145 ,  G06F9/30105 ,  G11C11/409 ,  G06F12/0246 ,  G06F12/0292 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30101 ,  G06F9/3818 ,  G06F9/30043 ,  G06F9/30032 ,  G06F16/322 ,  G06F16/9017 ,  G06F16/41 ,  G06F9/44505 ,  G06F3/0647

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

公开(公告)号：US20220413863A1

公开(公告)日：2022-12-29

申请号：US17901940

申请日：2022-09-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA ,  Rama VENKATASUBRAMANIAN

IPC: G06F9/30 ,  G06F16/31 ,  G06F9/38 ,  G06F9/445 ,  G06F12/02 ,  G06F16/901 ,  G06F16/41 ,  G11C11/409 ,  G06F12/0811 ,  G06F3/06 ,  G06F9/355

Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

公开(公告)号：US20220276965A1

公开(公告)日：2022-09-01

申请号：US17744810

申请日：2022-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

公开(公告)号：US20210365374A1

公开(公告)日：2021-11-25

申请号：US16882344

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  Pramod Kumar SWAMI ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F12/0811 ,  G06F12/10

Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

公开(公告)号：US20200371964A1

公开(公告)日：2020-11-26

申请号：US16882403

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F12/0811

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

公开(公告)号：US20200371934A1

公开(公告)日：2020-11-26

申请号：US16882229

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA ,  Peter Michael HIPPLEHEUSER

IPC: G06F12/0817 ,  G06F12/084 ,  G06F12/0811

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

公开(公告)号：US20200371930A1

公开(公告)日：2020-11-26

申请号：US16882216

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/128

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

公开(公告)号：US20200371923A1

公开(公告)日：2020-11-26

申请号：US16882305

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA ,  Peter Michael HIPPLEHEUSER

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/0895 ,  G06F12/0817 ,  G06F9/46 ,  G06F9/54

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

公开(公告)号：US20200371920A1

公开(公告)日：2020-11-26

申请号：US16882202

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

公开(公告)号：US20200371919A1

公开(公告)日：2020-11-26

申请号：US16882178

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F9/30 ,  G06F13/16 ,  G06F11/30

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.