SYSTEM, METHOD AND DEVICE FOR POWER AMPLIFICATION OF A SIGNAL IN AN INTEGRATED CIRCUIT
    1.
    发明申请
    SYSTEM, METHOD AND DEVICE FOR POWER AMPLIFICATION OF A SIGNAL IN AN INTEGRATED CIRCUIT 有权
    用于集成电路中信号功率放大的系统,方法和装置

    公开(公告)号:US20150214907A1

    公开(公告)日:2015-07-30

    申请号:US14165251

    申请日:2014-01-27

    Abstract: According to an aspect of present disclosure, a set of power amplifiers are used to amplify power of a signal for transmission. The signal powers from a set of power amplifiers are coupled to set of primary windings which are commonly coupled to a secondary winding such that the powers on the primary windings are additive in the secondary winding. A current path on the primary side is provided for flow of a current that is induced on at least one primary winding when a power amplifier coupled to that primary winding is in “off” state. As a result, the induced current is prevented from flowing in to the power amplifier that are in “on” state. Further, the current path isolates the power amplifiers from each other thereby enabling the power amplifiers to operate at the rated efficiency. In one embodiment, the current path is provided using a resistor network.

    Abstract translation: 根据本公开的一个方面,使用一组功率放大器来放大用于传输的信号的功率。 来自一组功率放大器的信号功率耦合到通常耦合到次级绕组的初级绕组组,使得初级绕组上的功率在次级绕组中是相加的。 当耦合到该初级绕组的功率放大器处于“关闭”状态时,提供初级侧上的电流路径用于在至少一个初级绕组上感应的电流的流动。 结果,防止感应电流流入处于“接通”状态的功率放大器。 此外,电流路径将功率放大器彼此隔离,从而使得功率放大器能够以额定效率工作。 在一个实施例中,使用电阻网络提供电流路径。

    System, method and device for power amplification of a signal in an integrated circuit
    3.
    发明授权
    System, method and device for power amplification of a signal in an integrated circuit 有权
    用于集成电路中信号功率放大的系统,方法和装置

    公开(公告)号:US09450546B2

    公开(公告)日:2016-09-20

    申请号:US14165251

    申请日:2014-01-27

    Abstract: According to an aspect of present disclosure, a set of power amplifiers are used to amplify power of a signal for transmission. The signal powers from a set of power amplifiers are coupled to set of primary windings which are commonly coupled to a secondary winding such that the powers on the primary windings are additive in the secondary winding. A current path on the primary side is provided for flow of a current that is induced on at least one primary winding when a power amplifier coupled to that primary winding is in “off” state. As a result, the induced current is prevented from flowing in to the power amplifier that are in “on” state. Further, the current path isolates the power amplifiers from each other thereby enabling the power amplifiers to operate at the rated efficiency. In one embodiment, the current path is provided using a resistor network.

    Abstract translation: 根据本公开的一个方面,使用一组功率放大器来放大用于传输的信号的功率。 来自一组功率放大器的信号功率耦合到通常耦合到次级绕组的初级绕组组,使得初级绕组上的功率在次级绕组中是相加的。 当耦合到该初级绕组的功率放大器处于“关闭”状态时,提供初级侧上的电流路径用于在至少一个初级绕组上感应的电流的流动。 结果,防止感应电流流入处于“接通”状态的功率放大器。 此外,电流路径将功率放大器彼此隔离,从而使得功率放大器能够以额定效率工作。 在一个实施例中,使用电阻网络提供电流路径。

    SWITCHED MODE POWER AMPLIFIER WITH IDEAL IQ COMBINING
    4.
    发明申请
    SWITCHED MODE POWER AMPLIFIER WITH IDEAL IQ COMBINING 审中-公开
    具有理想智能组合的开关模式功率放大器

    公开(公告)号:US20160126895A1

    公开(公告)日:2016-05-05

    申请号:US14529056

    申请日:2014-10-30

    Abstract: An I converter outputs I sign data and I magnitude data based on received I data. A Q converter outputs Q sign data and Q magnitude data based on received Q data. An I clock generates an I phase based ort the I sign data. A Q clock generates a Q phase based on the Q sign data. An I modulator generates an I magnitude pulse stream based on the I magnitude data. A Q modulator generates a Q magnitude pulse stream based on the Q magnitude data. A digital logic component generates an output signal based on the I phase, the I magnitude pulse stream, the Q phase and the Q magnitude pulse stream. A power amplifier generates an amplified signal based on the output signal.

    Abstract translation: I转换器根据接收到的I数据输出I符号数据和I幅度数据。 Q转换器基于接收的Q数据输出Q符号数据和Q幅度数据。 一个I时钟产生一个I相或ort的I符号数据。 Q时钟基于Q符号数据生成Q相。 I调制器基于I幅度数据生成I幅度脉冲流。 Q调制器基于Q幅度数据产生Q幅度脉冲流。 数字逻辑部件基于I相,I幅度脉冲流,Q相和Q幅度脉冲流产生输出信号。 功率放大器基于输出信号产生放大信号。

    DIGITAL CONTROLLED OSCILLATOR AND SWITCHABLE VARACTOR FOR HIGH FREQUENCY LOW NOISE OPERATION
    5.
    发明申请
    DIGITAL CONTROLLED OSCILLATOR AND SWITCHABLE VARACTOR FOR HIGH FREQUENCY LOW NOISE OPERATION 有权
    数字控制振荡器和高频低噪声操作的可切换变频器

    公开(公告)号:US20160112006A1

    公开(公告)日:2016-04-21

    申请号:US14518001

    申请日:2014-10-20

    CPC classification number: H03B5/1212 H03B5/1228 H03B5/1265

    Abstract: Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.

    Abstract translation: 提供了低噪声可切换变容二极管和数字控制振荡器(DCO)电路,用于在受控频率下产生交变信号,包括用于在控制信号处于第一状态时选择性地耦合变容二极管输出节点之间的两个电容器的第一晶体管,第二和第三晶体管 当控制信号处于第一状态时,选择性地将相应电容器和第一晶体管之间的第一和第二内部节点耦合到第三内部节点,并且逆变器从第一和第二内部节点断开以减轻相位噪声并且可操作地控制 根据控制信号,第三内部节点的电压。

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