Digital self-calibration for automatic offset cancellation

    公开(公告)号:US12081253B2

    公开(公告)日:2024-09-03

    申请号:US18352424

    申请日:2023-07-14

    CPC classification number: H04B1/16 H03F3/19 H03F3/245 H04L27/06 H03F2200/451

    Abstract: A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelope detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.

    Semiconductor device
    7.
    发明授权

    公开(公告)号:US12040323B2

    公开(公告)日:2024-07-16

    申请号:US17394252

    申请日:2021-08-04

    CPC classification number: H01L27/0647 H01L29/737 H03F3/19 H03F3/21

    Abstract: Each of cells arranged on a substrate surface along a first direction includes at least one unit transistor. Collector electrodes are arranged between two adjacent cells. A first cell, which is at least one of the cells, includes unit transistors arranged along the first direction. The unit transistors are connected in parallel to each another. In the first cell, the base electrode and the emitter electrode in each unit transistor are arranged along the first direction, and the order of arrangement of the base electrode and the emitter electrode is the same among the unit transistors. When looking at one first cell, a maximum value of distances in the first direction between the emitter electrodes of two adjacent unit transistors in the first cell being looked at is shorter than ½ of a shorter one of distances between the first cell being looked at and adjacent cells.

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