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    DELAY-COMPENSATING POWER MANAGEMENT CIRCUIT
    3.
    发明公开
    DELAY-COMPENSATING POWER MANAGEMENT CIRCUIT 审中-公开

    公开(公告)号：US20240136979A1

    公开(公告)日：2024-04-25

    申请号：US18402102

    申请日：2024-01-02

    Applicant: Qorvo US, Inc.

    Inventor： Nadim Khlat

    IPC: H03F1/02 ,  G05F1/46 ,  H03F1/32 ,  H03F3/195 ,  H03F3/24 ,  H04B1/40 ,  H04L27/36

    CPC classification number: H03F1/0222 ,  G05F1/461 ,  H03F1/32 ,  H03F3/195 ,  H03F3/24 ,  H04B1/40 ,  H04L27/366 ,  H03F2200/102 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/511

    Abstract: A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.

    Delay-compensating power management circuit
    4.
    发明授权
    Delay-compensating power management circuit 有权

    公开(公告)号：US11929712B2

    公开(公告)日：2024-03-12

    申请号：US17331756

    申请日：2021-05-27

    Applicant: Qorvo US, Inc.

    Inventor： Nadim Khlat

    IPC: H03F1/02 ,  G05F1/46 ,  H03F1/32 ,  H03F3/195 ,  H03F3/24 ,  H04B1/40 ,  H04L27/36

    CPC classification number: H03F1/0222 ,  G05F1/461 ,  H03F1/32 ,  H03F3/195 ,  H03F3/24 ,  H04B1/40 ,  H04L27/366 ,  H03F2200/102 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/511

    Abstract: A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.

    Inphase quadrature current selector amplifiers for wireless communication
    5.
    发明授权
    Inphase quadrature current selector amplifiers for wireless communication 有权

    公开(公告)号：US11894968B2

    公开(公告)日：2024-02-06

    申请号：US17589090

    申请日：2022-01-31

    Applicant: Swiftlink Technologies Inc.

    Inventor： Ayman Eltaliawy ,  Min-Yu Huang

    IPC: H04L27/36 ,  H03F3/24 ,  H03F3/16 ,  H04B1/38

    CPC classification number: H04L27/36 ,  H03F3/16 ,  H03F3/245 ,  H04B1/38 ,  H03F2200/336

    Abstract: A transmit in-phase quadrature (IQ) amplifier includes a common gain stage to receive an input signal and to generate an amplified signal. The amplifier includes an IQ poly-phase filter coupled to the common gain stage to receive the amplified signal from the common gain stage and outputs a four-phase signal. The amplifier includes an in-phase (I) phase switching gain stage coupled to the IQ poly-phase filter to receive I components of the four-phase signal and outputs an amplified phase switching I signal. The amplifier includes a quadrature (Q) phase switching gain stage coupled to the IQ poly-phase filter to receive Q components of the four-phase signal and outputs an amplified phase switching Q signal.

    Multi-level envelope tracking systems with adjusted voltage steps
    8.
    发明授权
    Multi-level envelope tracking systems with adjusted voltage steps 有权

    公开(公告)号：US11757414B2

    公开(公告)日：2023-09-12

    申请号：US17456952

    申请日：2021-11-30

    Applicant: Skyworks Solutions, Inc.

    Inventor： Serge Francois Drogi ,  Florinel G. Balteanu

    IPC: H03F1/30 ,  H03F1/02 ,  H03F3/24 ,  H03F3/195

    CPC classification number: H03F1/0227 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/171 ,  H03F2200/336 ,  H03F2200/451

    Abstract: Multi-level envelope tracking systems with adjusted voltage steps are provided. In certain embodiments, an envelope tracking system for generating a power amplifier supply voltage for a power amplifier is provided. The envelope tracking system includes a multi-level supply (MLS) DC-to-DC converter that outputs multiple regulated voltages, an MLS modulator that controls selection of the regulated voltages over time based on an envelope signal corresponding to an envelope of a radio frequency (RF) signal amplified by the power amplifier, and a modulator output filter coupled between an output of the MLS modulator and the power amplifier supply voltage. The envelope tracking system further includes a switching point adaptation circuit configured to control the voltage level of the regulated voltages outputted by the MLS DC-to-DC converter based on a power level of the RF signal.

    SYSTEM, METHOD, AND OUTPHASING POWER AMPLIFIER HAVING VECTOR GENERATOR AND IQ MODULATORS
    9.
    发明公开
    SYSTEM, METHOD, AND OUTPHASING POWER AMPLIFIER HAVING VECTOR GENERATOR AND IQ MODULATORS 审中-公开

    公开(公告)号：US20230231524A1

    公开(公告)日：2023-07-20

    申请号：US17576291

    申请日：2022-01-14

    Applicant: Rockwell Collins, Inc.

    Inventor： Timothy L. Kean

    IPC: H03F3/24

    CPC classification number: H03F3/245 ,  H03F2200/451 ,  H03F2200/336

    Abstract: A system may include a first IQ modulator configured to: based on an I and a Q, produce a zero to ninety degree variable phase shifted output signal that changes relative to an input envelope of an RF drive waveform of the RF drive. The system may include a first amplifier path configured to: output a first phase modulated signal. The system may include a second IQ modulator configured to: based on the I and the −Q, produce a zero to negative ninety degree variable phase shifted output signal that changes relative to the input envelope. The system may include a second amplifier path configured to: output a second phase modulated signal, wherein the second phase modulated signal is complementary to the first phase modulated signal. The system may include a vector generator configured to: generate the Q and the −Q for the first and second IQ modulators, respectively.

    Transformer-based current-reuse amplifier with embedded IQ generation for compact image rejection architecture in multi-band millimeter-wave 5G communication
    10.
    发明授权
    Transformer-based current-reuse amplifier with embedded IQ generation for compact image rejection architecture in multi-band millimeter-wave 5G communication 有权

    公开(公告)号：US11677430B2

    公开(公告)日：2023-06-13

    申请号：US16951330

    申请日：2020-11-18

    Applicant: SWIFTLINK TECHNOLOGIES INC.

    Inventor： Min-Yu Huang ,  Thomas Chen

    IPC: H04B1/40 ,  H03F3/45 ,  H03H11/32 ,  H04W84/04

    CPC classification number: H04B1/40 ,  H03F3/45179 ,  H03H11/32 ,  H03F2200/336 ,  H04W84/042

    Abstract: According to one embodiment, a transformer-based in-phase and quadrature (IQ) includes a differential balun having a first inductor and a second inductor. The first inductor has a first input terminal and a first output terminal. The second inductor has a second input terminal and a second output terminal. Additionally, the IQ generator circuit includes a third inductor magnetically coupled with the first inductor. The third inductor has a first isolation terminal and a third output terminal. The IQ generator circuit also includes a fourth inductor magnetically coupled with the second inductor. The fourth inductor has a second isolation terminal and a fourth output terminal. The IQ generator circuit additionally includes a first transistor coupled to the first input terminal of the first inductor. Further, the generator circuit includes a second transistor coupled to the second input terminal of the second inductor. The first transistor, the second transistor, the first inductor, and the second inductor form a part of a differential amplifier.

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