公开(公告)号：US20240143890A1

公开(公告)日：2024-05-02

申请号：US18050151

申请日：2022-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rakul VISWANATH ,  Sachin AITHAL ,  Gunvarun SUDAN

IPC: G06F30/394 ,  G06F30/347

CPC classification number: G06F30/394 ,  G06F30/347

Abstract: A circuit includes: channel signal chains; configuration registers including a configuration register for each of the channel signal chains; channel data registers including a channel data register for each of the channel signal chains; a first communication interface coupled to the configuration registers via a daisy-chain connection; a second communication interface coupled to the set of channel data registers via respective parallel connections; and routing interfaces including a routing interface for each of the channel signal chains, each of the routing interfaces having a routing data input, a daisy-chain connection input, a parallel connection input, first and second control inputs, and a routing data output.

公开(公告)号：US20220349748A1

公开(公告)日：2022-11-03

申请号：US17245436

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Rakul VISWANATH ,  Sachin AITHAL

IPC: G01J1/44

Abstract: An analog front-end circuit includes an array of pixel circuits. Each pixel circuit includes an event counter and a power consumption circuit. The event counter is configured to count photons incident at the pixel circuit. The power compensation circuit includes an event rate circuit and a current sink circuit. The event rate circuit is configured to determine a rate of photon detection events at the pixel circuit. The current sink circuit is configured to pass a compensation current selected based on the rate of photon detection events at the pixel circuit.

公开(公告)号：US20240313751A1

公开(公告)日：2024-09-19

申请号：US18589715

申请日：2024-02-28

Applicant: Texas Instruments Incorporated

Inventor： Sachin AITHAL ,  Anand H UDUPA ,  Raja Reddy PATUKURI ,  Sandeep OSWAL ,  Aatish CHANDAK ,  Vignesh SUBRAMANYA ,  Aravind MIRIYALA

IPC: H03K5/1252 ,  A61B5/00 ,  A61B5/349 ,  H03M1/12

CPC classification number: H03K5/1252 ,  A61B5/349 ,  A61B5/7217 ,  H03M1/12

Abstract: A circuit includes an interference frequency tracking circuit, a PLI synthesizer circuit, and a summing circuit. The interference frequency tracking circuit is configured to track a frequency of an interference signal derived from a target signal, and provide a frequency selection value representing the frequency of the interference signal. The PLI synthesizer circuit is configured to generate, based on the frequency selection value, a correction signal at the frequency of the interference signal, adjust a phase of the correction signal to match a phase of the interference signal in the target signal, and adjust an amplitude of the correction signal to match an amplitude of the interference signal in the target signal. The summing circuit is configured to subtract the correction signal from the target signal.