公开(公告)号：US20040008805A1

公开(公告)日：2004-01-15

申请号：US10376453

申请日：2003-02-26

Applicant: Texas Instruments Incorporated

Inventor： Liming Xiu ,  Zhihong You

IPC: H03D003/24

CPC classification number: H03L7/183 ,  H03L7/0996

Abstract: An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1, CLK2) at a desired frequency. The phase-locked loop (30) includes a voltage-controlled oscillator (37) that produces a number (N) of equally spaced clock phases at a frequency (fVCO) that depends also upon a programmable feedback frequency divider (38) and a prescale divider (32). The frequency synthesis circuit (20) generates the output clock (CLK1, CLK2) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (12), either itself or from a look-up table (13), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (null), by way of a minimization of the frequency error. The frequency of the output clock (CLK1, CLK2) can be generated in a jitter-free manner, since only integer values are used in the frequency synthesis circuit (20), at relatively low frequency error.

Abstract translation: 电子系统（10）包括锁相环（30）和频率合成电路（20），用于以期望的频率产生无抖动的输出时钟（CLK1，CLK2）。 锁相环（30）包括压控振荡器（37），该压控振荡器产生频率（fVCO）的等距间隔时钟相位数（N），该频率依赖于可编程反馈分频器（38）和预分频器 分频器（32）。 频率合成电路（20）在频率选择字（FREQ）的控制下以指示连续的时钟边沿之间的时钟相位数的频率产生输出时钟（CLK1，CLK2）。 本身或来自查找表（13）的中央处理单元（12）根据期望频率（f）产生反馈除法整数（M）和频率选择字（FREQ），借助于 最小化频率误差。 输出时钟（CLK1，CLK2）的频率可以以无抖动的方式产生，因为在频率合成电路（20）中以相对低的频率误差仅使用整数值。

公开(公告)号：US20030118142A1

公开(公告)日：2003-06-26

申请号：US10026489

申请日：2001-12-24

Applicant: Texas Instruments Incorporated

Inventor： Liming Xiu ,  Zhihong You

IPC: H03D003/24

CPC classification number: H03L7/16 ,  H03K2005/00208 ,  H03L7/0996

Abstract: A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed implementation of the phase-locked loop (25) includes a voltage-controlled oscillator (30) having an even number of differential stages (31) to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit (27) includes two adder legs that generate select signals applied to first and second multiplexers (40a, 40b), for selecting among the clock phases from the voltage-controlled oscillator (30). The outputs of the first and second multiplexers (40a, 40b) are applied to a two-to-one multiplexer (46) which is controlled by the output clock signal (CLK1), to drive clock edges to a T flip-flop (48) to produce the output clock signals (CLK1, CLK2). In another embodiment, more than two adder and register units (55) control corresponding multiplexers (56) for selecting clock phases from the voltage-controlled oscillator (30) for application to an output multiplexer (58), which is controlled by a clock control circuit (60) to apply the selected clock phases to the T flip-flop (62). In another embodiment, primary and phase-shifted frequency synthesis circuits (227, 327) receive initialization values (INIT1, INIT2) that establish the phase differential and ensure proper initialization.

Abstract translation: 公开了一种包括锁相环（25）和一个或多个频率合成电路（27; 77; 227; 237）的时钟合成电路（22）。 所公开的锁相环（25）的实现包括具有偶数个差分级（31）的压控振荡器（30），以产生偶数等间隔的时钟相位。 在一种布置中，频率合成电路（27）包括两个加法器支路，其产生施加到第一和第二多路复用器（40a，40b）的选择信号，用于在来自压控振荡器（30）的时钟相位之间进行选择。 第一和第二多路复用器（40a，40b）的输出被施加到由输出时钟信号（CLK1）控制的二对一复用器（46），以将时钟沿驱动到T触发器（48 ）以产生输出时钟信号（CLK1，CLK2）。 在另一实施例中，多于两个的加法器和寄存器单元（55）控制相应的多路复用器（56），用于从压控振荡器（30）中选择时钟相位，用于施加到输出多路复用器（58），其由时钟控制 电路（60）将所选择的时钟相位施加到T触发器（62）。 在另一个实施例中，初级和相移频率合成电路（227,327）接收初始化值（INIT1，INIT2），其建立相位差并确保适当的初始化。