公开(公告)号：US10374086B2

公开(公告)日：2019-08-06

申请号：US15369809

申请日：2016-12-05

申请人： The Regents of the University of California

发明人： Chenming Hu

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778

摘要： A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (CFE) is matched to the sum of the gate capacitance (CMOS) and the gate edge capacitance (CEDGE), wherein the gate edge capacitance (CEDGE) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

公开(公告)号：US20170162702A1

公开(公告)日：2017-06-08

申请号：US15369809

申请日：2016-12-05

申请人： The Regents of the University of California

发明人： Chenming Hu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L29/78391 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/775 ,  H01L29/778 ,  H01L29/785 ,  H01L29/78696

摘要： A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (CFE) is matched to the sum of the gate capacitance (CMOS) and the gate edge capacitance (CEDGE), wherein the gate edge capacitance (CEDGE) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.