公开(公告)号：US20240028884A1

公开(公告)日：2024-01-25

申请号：US18255346

申请日：2021-10-04

申请人： The Regents of the University of California

发明人： Steven L. MORAN ,  Subramanian S. IYER ,  Zhe WAN ,  Sudhakar PAMARTI

IPC分类号： G06N3/065 ,  H01L29/792 ,  H10B43/00

CPC分类号： G06N3/065 ,  H01L29/792 ,  H10B43/00

摘要： Present implementations can include a system with a transistor array including a plurality of charge-trap transistors, the charge-trap transistors being operatively coupled with corresponding input nodes, and a neural integrator including a first integrator node and a second integrator node operatively coupled with the transistor array, and generating an output corresponding to a neuron of a neural network system. Present implementations can include a neural integrator with a first integrator node operatively coupled with a first charge-trap transistor of a transistor array, a second integrator node operatively coupled with a second charge-trap transistor of the transistor array, the second charge-trap transistor being operatively coupled with the first charge-trap transistor, and a capacitor operatively coupled with the first integrator node and the second integrator node, and operable to generate an output based on a first voltage at the first integrator node and a second voltage at the second integrator node.