公开(公告)号：US20240147716A1

公开(公告)日：2024-05-02

申请号：US18404676

申请日：2024-01-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC分类号： H10B41/30 ,  H01L21/28 ,  H01L21/306 ,  H01L21/321 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/66 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30

CPC分类号： H10B41/30 ,  H01L21/30604 ,  H01L21/3212 ,  H01L21/823462 ,  H01L27/105 ,  H01L29/40114 ,  H01L29/66545 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30 ,  H10B10/18

摘要： An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

公开(公告)号：US20230209829A1

公开(公告)日：2023-06-29

申请号：US18176656

申请日：2023-03-01

申请人： KIOXIA CORPORATION

发明人： Toshifumi MINAMI ,  Atsuhiro SATO ,  Keisuke YONEHAMA ,  Yasuyuki BABA ,  Hiroshi SHINOHARA ,  Hideyuki KAMATA ,  Teppei HIGASHITSUJI

IPC分类号： H10B43/27 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US20240306393A1

公开(公告)日：2024-09-12

申请号：US18666035

申请日：2024-05-16

申请人： Kioxia Corporation

发明人： Toshifumi MINAMI ,  Atsuhiro SATO ,  Keisuke YONEHAMA ,  Yasuyuki BABA ,  Hiroshi SHINOHARA ,  Hideyuki KAMATA ,  Teppei HIGASHITSUJI

IPC分类号： H10B43/27 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US20240028884A1

公开(公告)日：2024-01-25

申请号：US18255346

申请日：2021-10-04

申请人： The Regents of the University of California

发明人： Steven L. MORAN ,  Subramanian S. IYER ,  Zhe WAN ,  Sudhakar PAMARTI

IPC分类号： G06N3/065 ,  H01L29/792 ,  H10B43/00

CPC分类号： G06N3/065 ,  H01L29/792 ,  H10B43/00

摘要： Present implementations can include a system with a transistor array including a plurality of charge-trap transistors, the charge-trap transistors being operatively coupled with corresponding input nodes, and a neural integrator including a first integrator node and a second integrator node operatively coupled with the transistor array, and generating an output corresponding to a neuron of a neural network system. Present implementations can include a neural integrator with a first integrator node operatively coupled with a first charge-trap transistor of a transistor array, a second integrator node operatively coupled with a second charge-trap transistor of the transistor array, the second charge-trap transistor being operatively coupled with the first charge-trap transistor, and a capacitor operatively coupled with the first integrator node and the second integrator node, and operable to generate an output based on a first voltage at the first integrator node and a second voltage at the second integrator node.

公开(公告)号：US11837299B2

公开(公告)日：2023-12-05

申请号：US17716122

申请日：2022-04-08

申请人： Chen-Feng Chang

发明人： Chen-Feng Chang ,  Tien-Sheng Chao

IPC分类号： G11C16/04 ,  G11C17/12 ,  G11C11/56 ,  H10B20/20 ,  H10B43/00

CPC分类号： G11C17/12 ,  G11C11/5671 ,  G11C16/0466 ,  H10B20/20 ,  H10B43/00

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.

公开(公告)号：US20240332385A1

公开(公告)日：2024-10-03

申请号：US18739179

申请日：2024-06-10

申请人： LONGITUDE FLASH MEMORY SOLUTIONS LTD.

发明人： Igor Polishchuk ,  Sagy Charel Levy ,  Krishnaswamy Ramkumar

IPC分类号： H01L29/423 ,  B82Y10/00 ,  G11C16/04 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

CPC分类号： H01L29/4234 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02532 ,  H01L21/02595 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

摘要： An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

公开(公告)号：US12080363B2

公开(公告)日：2024-09-03

申请号：US17722534

申请日：2022-04-18

申请人： Chen-Feng Chang

发明人： Chen-Feng Chang ,  Tien-Sheng Chao

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C17/12 ,  H10B20/20 ,  H10B43/00 ,  H01L29/06 ,  H01L29/423

CPC分类号： G11C17/12 ,  G11C11/5671 ,  G11C16/0466 ,  H10B20/20 ,  H10B43/00 ,  H01L29/0673 ,  H01L29/42392

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode. A multiplicity of M nanowire channels is mounted between the first electrode and the second electrode, and M is a positive integer greater than one. The operation method breaks multiple states of the multi-bits read only memory. The multiple states are programmable and include an ith state, and 1≤ i≤ M. The aforementioned states allow storage of multiple bits on the read only memory, instead of just storing a single bit on the read only memory.

公开(公告)号：US12009401B2

公开(公告)日：2024-06-11

申请号：US17952796

申请日：2022-09-26

申请人： LONGITUDE FLASH MEMORY SOLUTIONS LTD.

发明人： Igor Polishchuk ,  Sagy Charel Levy ,  Krishnaswamy Ramkumar

IPC分类号： H01L27/11526 ,  B82Y10/00 ,  G11C16/04 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

CPC分类号： H01L29/4234 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02532 ,  H01L21/02595 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

摘要： An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

公开(公告)号：US11903191B2

公开(公告)日：2024-02-13

申请号：US17231204

申请日：2021-04-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC分类号： H10B41/30 ,  H01L21/28 ,  H01L27/105 ,  H01L21/8234 ,  H01L29/66 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30 ,  H01L21/306 ,  H01L21/321 ,  H10B10/00

CPC分类号： H10B41/30 ,  H01L21/30604 ,  H01L21/3212 ,  H01L21/823462 ,  H01L27/105 ,  H01L29/40114 ,  H01L29/66545 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30 ,  H10B10/18

摘要： An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

公开(公告)号：US11730000B2

公开(公告)日：2023-08-15

申请号：US17493502

申请日：2021-10-04

申请人： Sunrise Memory Corporation

发明人： Eli Harari ,  Wu-Yi Chien

IPC分类号： H10B69/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/30 ,  H10B43/00 ,  H10B43/20 ,  H10B43/30 ,  G11C16/04 ,  C25B11/051 ,  C25B3/25 ,  C25B11/075 ,  B01J37/16 ,  C01G3/00 ,  C07C1/12 ,  C22B15/00 ,  C30B7/14 ,  C30B29/02 ,  C30B29/64

CPC分类号： H10B69/00 ,  B01J37/16 ,  C01G3/00 ,  C07C1/12 ,  C22B15/00 ,  C25B3/25 ,  C25B11/051 ,  C25B11/075 ,  C30B7/14 ,  C30B29/02 ,  C30B29/64 ,  G11C16/04 ,  H01L23/528 ,  H10B41/27 ,  H10B41/30 ,  H10B43/00 ,  H10B43/20 ,  H10B43/30 ,  C07C2523/72

摘要： A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.