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1.发明公开公开(公告)号：US20230225225A1
公开(公告)日：2023-07-13
申请号：US18000377
申请日：2021-05-27
发明人： Yu-Tao YANG , Subramanian S. IYER
摘要： Example implementations include a method of manufacturing a quantum computing device, by depositing a superconducting electrode layer on at least a portion of a superconducting wafer, forming a plurality of electrode pads on the superconducting electrode layer, depositing an electrode bonding interlayer on the electrode pads, singulating the superconducting wafer into a first superconducting die including a first electrode pad among the plurality and a second superconducting die including a second electrode pad among the plurality, and integrating the first superconducting die with the second superconducting die at a bonding interface between the first electrode pad and the second electrode pad.
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公开(公告)号：US20210074648A1
公开(公告)日：2021-03-11
申请号：US16965934
申请日：2019-01-30
IPC分类号： H01L23/538 , H01L21/48
摘要： A flexible device includes: (1) a flexible substrate; and (2) an interconnect disposed over the flexible substrate, wherein the interconnect has a varying vertical displacement along its length, relative to a top surface of the flexible substrate.
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3.发明公开公开(公告)号：US20240028884A1
公开(公告)日：2024-01-25
申请号：US18255346
申请日：2021-10-04
IPC分类号： G06N3/065 , H01L29/792 , H10B43/00
CPC分类号： G06N3/065 , H01L29/792 , H10B43/00
摘要： Present implementations can include a system with a transistor array including a plurality of charge-trap transistors, the charge-trap transistors being operatively coupled with corresponding input nodes, and a neural integrator including a first integrator node and a second integrator node operatively coupled with the transistor array, and generating an output corresponding to a neuron of a neural network system. Present implementations can include a neural integrator with a first integrator node operatively coupled with a first charge-trap transistor of a transistor array, a second integrator node operatively coupled with a second charge-trap transistor of the transistor array, the second charge-trap transistor being operatively coupled with the first charge-trap transistor, and a capacitor operatively coupled with the first integrator node and the second integrator node, and operable to generate an output based on a first voltage at the first integrator node and a second voltage at the second integrator node.
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公开(公告)号：US20230238476A1
公开(公告)日：2023-07-27
申请号：US18007697
申请日：2021-06-01
CPC分类号： H01L33/0093 , H01L25/167 , H01L24/24 , H01L24/82 , H01L24/95 , H01L33/56 , H01L33/32
摘要： Example implementations include a method of mass transfer of display elements, by depositing one or more resist layers between one or more display elements disposed on a photoemitting layer, depositing at least one stress buffer layer between the resist layers, removing the resist layer and at least a portion of the photoemitting layer disposed in contact with the resist layers to form resist layer gaps on a wafer substrate, dicing the wafer substrate at the resist layer gaps to form at least one wafer die, separating the wafer substrate from the display elements by irradiation at corresponding first surfaces of the display elements, removing the stress buffer layers from the wafer die, and bonding the portion of the display elements to a first handler substrate at one or more electrode pads of the portion of the display elements.
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公开(公告)号：US20190287927A1
公开(公告)日：2019-09-19
申请号：US16345135
申请日：2017-10-30
IPC分类号： H01L23/00 , H01L23/538 , H01L21/56
摘要： A fan-out wafer level package includes: (1) a flexible substrate; (2) a semiconductor component embedded in the flexible substrate, the semiconductor component including an active surface that is exposed from the flexible substrate, the semiconductor component including a bonding pad adjacent to the active surface; (3) a stress buffer layer disposed over the flexible substrate and the semiconductor component, the stress buffer layer defining an opening exposing the bonding pad of the semiconductor component; and (4) an interconnect disposed over the stress buffer layer and including a portion extending into the opening of the stress buffer layer to electrically connect to the bonding pad of the semiconductor component.
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