公开(公告)号：US12007890B2

公开(公告)日：2024-06-11

申请号：US18139785

申请日：2023-04-26

Applicant: The Trustees of Princeton University

Inventor： Naveen Verma ,  Hossein Valavi ,  Hongyang Jia

IPC: G06F12/06 ,  G06F12/02 ,  G06F17/16 ,  G06N3/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/419 ,  H03K19/20

CPC classification number: G06F12/0607 ,  G06F12/0207 ,  G06F17/16 ,  G06N3/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/419 ,  H03K19/20 ,  G06F2212/454

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

公开(公告)号：US20180349142A1

公开(公告)日：2018-12-06

申请号：US15614081

申请日：2017-06-05

Applicant: The Trustees of Princeton University

Inventor： Hongyang Jia ,  Naveen Verma

IPC: G06F9/30 ,  G06F17/30 ,  G06N5/04

Abstract: A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module. An automatic-programming & classifier training module may be configured to receive input-output feature data and training labels and generate gene code and a classifier model.

公开(公告)号：US11669446B2

公开(公告)日：2023-06-06

申请号：US17252521

申请日：2019-06-18

Applicant: The Trustees of Princeton University

Inventor： Naveen Verma ,  Hossein Valavi ,  Hongyang Jia

IPC: G06F12/06 ,  G06F17/16 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/419 ,  H03K19/20 ,  G06N3/065 ,  G06F12/02 ,  G11C11/4074

CPC classification number: G06F12/0607 ,  G06F12/0207 ,  G06F17/16 ,  G06N3/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/419 ,  H03K19/20 ,  G06F2212/454

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

公开(公告)号：US11500635B2

公开(公告)日：2022-11-15

申请号：US15614081

申请日：2017-06-05

Applicant: The Trustees of Princeton University

Inventor： Hongyang Jia ,  Naveen Verma

IPC: G06F9/30 ,  G06F16/28 ,  G06N20/10 ,  G06N3/12

Abstract: A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module. An automatic-programming & classifier training module may be configured to receive input-output feature data and training labels and generate gene code and a classifier model.