公开(公告)号：US20100118870A1

公开(公告)日：2010-05-13

申请号：US12451995

申请日：2008-06-06

申请人： Serge Defrance ,  Thierry Tapie ,  Philippe Rio

发明人： Serge Defrance ,  Thierry Tapie ,  Philippe Rio

IPC分类号： H04L12/56 ,  H04J3/06

CPC分类号： H04N21/64322 ,  H03L7/091 ,  H04N21/242

摘要： The present invention pertains to a device able to send packets in a packet communication network comprising at least two stations, the said device comprising means for: -extracting image pips on the basis of a synchronization signal; -initializing a first counter on the basis of the said image pips; -initializing a second counter every “m” zero-crossings of the first counter; -sampling the second counter every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the said network; and -sending packets containing the samples in the network, characterized in that it comprises, furthermore, means for: receiving at least one phase deviation value Δφ to be applied; -sending the phase deviation value Δφ in the network. The present invention also pertains to a reception device able to receive packets in a packet communication network comprising at least two stations.

摘要翻译： 本发明涉及一种能够在包括至少两个站的分组通信网络中发送分组的设备，所述设备包括用于：基于同步信号提取图像点的装置; - 基于所述图像点初始化第一计数器; - 在第一计数器的每“m”个零交叉点初始化第二计数器; 每个周期Tsmp采样第二计数器，其中Tsmp从在所述网络的所有站同步的时基发出; 以及包含所述网络中的样本的发送分组，其特征在于，其还包括用于：接收至少一个相位偏差值＆Dgr;＆phgr; 应用; 发送相位偏差值＆Dgr;＆phgr; 在网络中。 本发明还涉及能够在包括至少两个站的分组通信网络中接收分组的接收设备。

公开(公告)号：US09467722B2

公开(公告)日：2016-10-11

申请号：US12460996

申请日：2009-07-28

申请人： Thierry Tapie ,  Serge Defrance ,  Philippe Rio

发明人： Thierry Tapie ,  Serge Defrance ,  Philippe Rio

IPC分类号： G06F15/16 ,  H04N21/242 ,  H03L7/18 ,  H04N21/2368 ,  H04N21/434 ,  H04N21/8547 ,  H04J3/06

CPC分类号： H04N21/242 ,  H03L7/18 ,  H04J3/0664 ,  H04N21/2368 ,  H04N21/4341 ,  H04N21/8547

摘要： The present invention relates to the domain of synchronization of items of equipment connected by a packet switching network. It relates more specifically to a system for generation of a synchronization signal (PIPA, PIPB) and a clock signal (CLK_outA, CLK_outB) by a slave station (SA, SB) connected to a master station (SM) via a packet switching network. The master station (SM) is conformed to produce a master clock signal (CLKM) of frequency FM and a master synchronization signal (PIPM). The master synchronization signal (PIPM) is in phase with the master clock signal (SM). The slave station (SA, SB) comprises the primary synthesis means (SM1A, SM1B) producing a slave periodic signal TICKSA, TICKSB), the periodic signal (TICKSA, TICKSB) is in phase with the master clock signal (CLKM). According to the invention, the slave station (SA, SB) also comprises the secondary means of synthesis (SM2A, SM2B) to synthesize a clock signal (CLK_outA, CLK_outB) and the synchronization signal (PIPA, PIPB) and in that said clock signal (CLK_outA, CLK_outB) and said synchronization signal (PIPA, PIPB) are in phase with said signal (TICKSA, TICKSB).

摘要翻译： 本发明涉及通过分组交换网络连接的设备项目的同步领域。 更具体地说，涉及通过分组交换网络连接到主站（SM）的从站（SA，SB）产生同步信号（PIPA，PIPB）和时钟信号（CLK_outA，CLK_outB）的系统。 主站（SM）符合产生频率FM的主时钟信号（CLKM）和主同步信号（PIPM）。 主同步信号（PIPM）与主时钟信号（SM）同相。 从站（SA，SB）包括产生从周期信号TICKSA，TICKSB的初级合成装置（SM1A，SM1B），周期信号（TICKSA，TICKSB）与主时钟信号（CLKM）同相。 根据本发明，从站（SA，SB）还包括合成时钟信号（CLK_outA，CLK_outB）和同步信号（PIPA，PIPB）的辅助合成装置（SM2A，SM2B），并且所述时钟信号 （CLK_outA，CLK_outB）和所述同步信号（PIPA，PIPB）与所述信号（TICKSA，TICKSB）同相。

公开(公告)号：US20100042748A1

公开(公告)日：2010-02-18

申请号：US12460996

申请日：2009-07-28

申请人： Thierry Tapie ,  Serge Defrance ,  Philippe Rio

发明人： Thierry Tapie ,  Serge Defrance ,  Philippe Rio

IPC分类号： G06F15/16

CPC分类号： H04N21/242 ,  H03L7/18 ,  H04J3/0664 ,  H04N21/2368 ,  H04N21/4341 ,  H04N21/8547

摘要： The present invention relates to the domain of synchronization of items of equipment connected by a packet switching network. It relates more specifically to a system for generation of a synchronization signal (PIPA, PIPB) and a clock signal (CLK_outA, CLK_outB) by a slave station (SA, SB) connected to a master station (SM) via a packet switching network. The master station (SM) is conformed to produce a master clock signal (CLKM) of frequency FM and a master synchronization signal (PIPM). The master synchronization signal (PIPM) is in phase with the master clock signal (SM). The slave station (SA, SB) comprises the primary synthesis means (SM1A, SM1B) producing a slave periodic signal TICKSA, TICKSB), the periodic signal (TICKSA, TICKSB) is in phase with the master clock signal (CLKM). According to the invention, the slave station (SA, SB) also comprises the secondary means of synthesis (SM2A, SM2B) to synthesize a clock signal (CLK_outA, CLK_outB) and the synchronization signal (PIPA, PIPB) and in that said clock signal (CLK_outA, CLK_outB) and said synchronization signal (PIPA, PIPB) are in phase with said signal (TICKSA, TICKSB).

摘要翻译： 本发明涉及通过分组交换网络连接的设备项目的同步领域。 更具体地说，涉及通过分组交换网络连接到主站（SM）的从站（SA，SB）产生同步信号（PIPA，PIPB）和时钟信号（CLK_outA，CLK_outB）的系统。 主站（SM）符合产生频率FM的主时钟信号（CLKM）和主同步信号（PIPM）。 主同步信号（PIPM）与主时钟信号（SM）同相。 从站（SA，SB）包括产生从周期信号TICKSA，TICKSB的初级合成装置（SM1A，SM1B），周期信号（TICKSA，TICKSB）与主时钟信号（CLKM）同相。 根据本发明，从站（SA，SB）还包括合成时钟信号（CLK_outA，CLK_outB）和同步信号（PIPA，PIPB）的辅助合成装置（SM2A，SM2B），并且所述时钟信号 （CLK_outA，CLK_outB）和所述同步信号（PIPA，PIPB）与所述信号（TICKSA，TICKSB）同相。

公开(公告)号：US08170012B2

公开(公告)日：2012-05-01

申请号：US12451995

申请日：2008-06-06

申请人： Serge Defrance ,  Thierry Tapie ,  Philippe Rio

发明人： Serge Defrance ,  Thierry Tapie ,  Philippe Rio

IPC分类号： H04L12/28 ,  H04J3/00 ,  H04N9/475

CPC分类号： H04N21/64322 ,  H03L7/091 ,  H04N21/242

摘要： A device is operative to send packets in a packet communication network having at least two stations. According to an exemplary embodiment, the device operates by: extracting image pips on the basis of a synchronization signal; initializing a first counter on the basis of the the image pips; initializing a second counter according to zero-crossings of the first counter; sampling the second counter every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the network; sending packets containing the samples of the second counter in the network; receiving at least one phase deviation value Δφ to be applied; and sending the at least one phase deviation value Δφ in the network. The present invention also pertains to a device operative to receive packets in a packet communication network having at least two stations.

摘要翻译： 一种设备可操作以在具有至少两个站的分组通信网络中发送分组。 根据示例性实施例，设备通过以下方式操作：基于同步信号提取图像点; 基于图像点初始化第一计数器; 根据第一计数器的零交叉来初始化第二计数器; 每个周期Tsmp采样第二个计数器，其中Tsmp从在网络的所有站同步的时基发出; 发送包含网络中第二个计数器的样本的数据包; 接收至少一个相位偏差值＆Dgr;＆phgr; 应用; 并发送所述至少一个相位偏差值＆Dgr;＆phgr; 在网络中。 本发明还涉及一种在具有至少两个站的分组通信网络中接收分组的设备。

公开(公告)号：US08237644B2

公开(公告)日：2012-08-07

申请号：US10589930

申请日：2005-02-01

申请人： Patrick Morvan ,  Philippe Rio ,  Maurice Fritsch ,  Didier Doyen

发明人： Patrick Morvan ,  Philippe Rio ,  Maurice Fritsch ,  Didier Doyen

IPC分类号： G09G3/36

CPC分类号： G09G3/3659 ,  G09G3/2018 ,  G09G3/2081 ,  G09G2300/0804 ,  G09G2300/0809 ,  G09G2300/0814 ,  G09G2310/0205 ,  G09G2310/0235 ,  G09G2310/0251

摘要： The present invention relates to the architecture of a valve of liquid crystal elements with pixel memory for front or rear projector. The valve comprises elements arranged in rows and columns, each of the elements comprising a liquid crystal controlled by drive means so as to display video information relating to at least one image. According to the invention, one seeks to reduce the size of the drive means of the liquid crystals. Accordingly, capacitors and transistors of the drive means are shared in common between several elements of the valve. The video information intended to be displayed by each of the elements of the valve is coded as a common value shared by a group of at least two adjacent elements of the valve and a specific value before being transmitted to the valve.

摘要翻译： 本发明涉及具有用于前投影机或后投影仪的像素存储器的液晶元件的阀的结构。 阀包括以行和列布置的元件，每个元件包括由驱动装置控制的液晶，以便显示与至少一个图像有关的视频信息。 根据本发明，寻求减小液晶驱动装置的尺寸。 因此，驱动装置的电容器和晶体管在阀的若干元件之间共同共用。 旨在由阀的每个元件显示的视频信息被编码为由阀的至少两个相邻元件的一组共同的共同值，并且在被传送到阀之前是特定值。

公开(公告)号：US20070279348A1

公开(公告)日：2007-12-06

申请号：US10589930

申请日：2005-02-01

申请人： Patrick Morvan ,  Philippe Rio ,  Maurice Fritsch ,  Didier Doyen

发明人： Patrick Morvan ,  Philippe Rio ,  Maurice Fritsch ,  Didier Doyen

IPC分类号： G09G3/36

CPC分类号： G09G3/3659 ,  G09G3/2018 ,  G09G3/2081 ,  G09G2300/0804 ,  G09G2300/0809 ,  G09G2300/0814 ,  G09G2310/0205 ,  G09G2310/0235 ,  G09G2310/0251

摘要： The present invention relates to the architecture of a valve of liquid crystal elements with pixel memory for front or rear projector. The valve comprises elements arranged in rows and columns, each of the elements comprising a liquid crystal controlled by drive means so as to display video information relating to at least one image. According to the invention, one seeks to reduce the size of the drive means of the liquid crystals. Accordingly, capacitors and transistors of the drive means are shared in common between several elements of the valve. The video information intended to be displayed by each of the elements of the valve is coded as a common value shared by a group of at least two adjacent elements of the valve and a specific value before being transmitted to the valve.

摘要翻译： 本发明涉及具有用于前投影机或后投影仪的像素存储器的液晶元件的阀的结构。 阀包括以行和列布置的元件，每个元件包括由驱动装置控制的液晶，以便显示与至少一个图像有关的视频信息。 根据本发明，寻求减小液晶驱动装置的尺寸。 因此，驱动装置的电容器和晶体管在阀的若干元件之间共同共用。 旨在由阀的每个元件显示的视频信息被编码为由阀的至少两个相邻元件的一组共同的共同值，并且在被传送到阀之前是特定值。