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    Power efficient instruction prefetch mechanism
    1.
    发明授权
    Power efficient instruction prefetch mechanism 有权
    高效的指令预取机制

    公开(公告)号：US08661229B2

    公开(公告)日：2014-02-25

    申请号：US12434804

    申请日：2009-05-04

    申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3844 ,  G06F9/3804

    摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

    摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

    Power Efficient Instruction Prefetch Mechanism
    2.
    发明申请
    Power Efficient Instruction Prefetch Mechanism 有权
    高效率指令预取机制

    公开(公告)号：US20090210663A1

    公开(公告)日：2009-08-20

    申请号：US12434804

    申请日：2009-05-04

    申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3804

    摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

    摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

    Power efficient instruction prefetch mechanism
    3.
    发明授权
    Power efficient instruction prefetch mechanism 有权
    高效的指令预取机制

    公开(公告)号：US07587580B2

    公开(公告)日：2009-09-08

    申请号：US11050932

    申请日：2005-02-03

    申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3844 ,  G06F9/3804

    摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

    摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

    Method and apparatus for managing cache partitioning using a dynamic boundary
    4.
    发明授权
    Method and apparatus for managing cache partitioning using a dynamic boundary 有权
    使用动态边界管理缓存分区的方法和装置

    公开(公告)号：US07650466B2

    公开(公告)日：2010-01-19

    申请号：US11233575

    申请日：2005-09-21

    申请人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Robert Douglas Clancy ,  Victor Roberts Augsburg

    发明人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Robert Douglas Clancy ,  Victor Roberts Augsburg

    IPC分类号： G06F12/00

    CPC分类号： G06F12/126

    摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.

    摘要翻译： 管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。 例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。 响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。 响应于解锁写入，第二个指针是高级的。 第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。 因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

    Speculative Instruction Issue in a Simultaneously Multithreaded Processor
    6.
    发明申请
    Speculative Instruction Issue in a Simultaneously Multithreaded Processor 有权
    同时多线程处理器中的推测指令

    公开(公告)号：US20080189521A1

    公开(公告)日：2008-08-07

    申请号：US12105091

    申请日：2008-04-17

    申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott Mcilvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

    发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott Mcilvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3836 ,  G06F9/3826 ,  G06F9/3851

    摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

    摘要翻译： 一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。 在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。 指令问题逻辑根据当指令到达要求管道中的阶段时所需操作数将可用的概率推测性地发出给定线程的指令。 如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。 一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

    Speculative instruction issue in a simultaneously multithreaded processor
    7.
    发明授权
    Speculative instruction issue in a simultaneously multithreaded processor 失效
    同时多线程处理器中的推测性指令问题

    公开(公告)号：US07366877B2

    公开(公告)日：2008-04-29

    申请号：US10664384

    申请日：2003-09-17

    申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

    发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3826 ,  G06F9/3851

    摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

    摘要翻译： 一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。 在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。 指令问题逻辑根据当指令到达需要的流水线中的阶段时，基于所需操作数将可用的概率来推测来自给定线程的指令。 如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。 一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

    System and method wherein conditional instructions unconditionally provide output
    8.
    发明授权
    System and method wherein conditional instructions unconditionally provide output 有权
    其中条件指令无条件地提供输出的系统和方法

    公开(公告)号：US07624256B2

    公开(公告)日：2009-11-24

    申请号：US11106803

    申请日：2005-04-14

    申请人： Thomas Andrew Sartorius ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F13/00

    CPC分类号： G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

    摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

    摘要翻译： 一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便 它无条件地向目标提供输出。 条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。 评估条件。 如果满足条件，则执行操作并将操作结果输出到目标。 如果条件不满足，则将先前值输出到目标。 后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

    Latency insensitive FIFO signaling protocol
    9.
    发明授权
    Latency insensitive FIFO signaling protocol 有权
    延迟不敏感的FIFO信令协议

    公开(公告)号：US07454538B2

    公开(公告)日：2008-11-18

    申请号：US11128135

    申请日：2005-05-11

    申请人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

    发明人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

    IPC分类号： G06F3/00

    CPC分类号： G06F13/4059 ,  G06F5/06 ,  G06F2205/126

    摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

    摘要翻译： 来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。 源端计数器跟踪FIFO中可用的空间。 在公开的示例中，初始计数器值对应于FIFO深度。 响应于来自源域的数据就绪信号，计数器无延迟地递减。 响应于来自接收器域的信令从FIFO读取数据，计数器递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器指示FIFO已满时，源可能再发送一次数据。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

    Latency insensitive FIFO signaling protocol
    10.
    发明授权
    Latency insensitive FIFO signaling protocol 有权
    延迟不敏感的FIFO信令协议

    公开(公告)号：US07725625B2

    公开(公告)日：2010-05-25

    申请号：US12179970

    申请日：2008-07-25

    申请人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

    发明人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

    IPC分类号： G06F3/00

    CPC分类号： G06F13/4059 ,  G06F5/06 ,  G06F2205/126

    摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

    摘要翻译： 来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。 源端计数器跟踪FIFO中可用的空间。 在公开的示例中，初始计数器值对应于FIFO深度。 响应于来自源域的数据就绪信号，计数器无延迟地递减。 响应于来自接收器域的信令从FIFO读取数据，计数器递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器指示FIFO已满时，源可能再发送一次数据。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。