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公开(公告)号：US06341079B1
公开(公告)日：2002-01-22
申请号：US09863848
申请日：2001-05-23
申请人： Thomas B. Chadwick
发明人： Thomas B. Chadwick
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G11C15/04 , G11C15/043
摘要： A content addressable memory device comprises a NAND-NOR chain comprised an alternating sequence of NAND and NOR stages; the NAND stages, each including a first CAM cell comprising a first memory cell that stores a first data bit and a first compare cell that compares the first data bit with a first compare bit and generates a first compare signal indicating whether the first data bit matches the first compare bit and a logical NAND gate that combines the first compare signals of other first CAM cells in the NAND stage; the NOR stages, each including a second CAM cell comprising a second memory cell that stores a second data bit and a second compare cell that compares the second data bit with a second compare bit and generates a second compare signal indicating whether the second data bit matches the second compare bit and a logical NOR gate that combines the second compare signals of other second CAM cells in the NOR stage; and the NAND-NOR chain generating a match signal indicating a match of all the compare bits to all the data bits in the content addressable memory device.
摘要翻译： 内容可寻址存储器件包括NAND-NOR链，其包括NAND和NOR级的交替序列; NAND阶段，每个包括第一CAM单元，其包括存储第一数据位的第一存储器单元和将第一数据位与第一比较位进行比较的第一比较单元，并产生指示第一数据位是否匹配的第一比较信号 第一比较位和逻辑与非门，其组合NAND阶段中的其它第一CAM单元的第一比较信号; NOR级，每个包括第二CAM单元，其包括存储第二数据位的第二存储器单元和将第二数据位与第二比较位进行比较的第二比较单元，并产生指示第二数据位是否匹配的第二比较信号 第二比较位和逻辑“或非”门，其组合NOR阶段中的其它第二CAM单元的第二比较信号; 并且NAND-NOR链产生指示所有比较位与内容可寻址存储器件中的所有数据位匹配的匹配信号。
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公开(公告)号：US06920525B2
公开(公告)日：2005-07-19
申请号：US10199788
申请日：2002-07-19
申请人： Thomas B. Chadwick , Tarl S. Gordon , Rahul K. Nadkarni , Michael R. Ouellette , Jeremy Rowland
发明人： Thomas B. Chadwick , Tarl S. Gordon , Rahul K. Nadkarni , Michael R. Ouellette , Jeremy Rowland
CPC分类号： G11C29/816 , G11C15/00 , G11C29/848
摘要： A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.
摘要翻译： 介绍了实现半导体存储器的字线和匹配线转向的局部字线冗余架构和方法，特别是用于内容寻址存储器（CAM）的本地字线冗余架构和方法。 根据本发明，执行本地字线冗余的方法包括：通过使用BIST测试，存储结果，比较失败的读地址数据和失败的匹配行地址数据，以确定冗余是否可能，如果是，则存储 冗余修复数据模式和初始化时的装载，从而激活冗余转向。
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3.发明授权公开(公告)号：US06711040B2
公开(公告)日：2004-03-23
申请号：US10353119
申请日：2003-01-28
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.
摘要翻译： 用于改善内容可寻址存储器阵列的方法和结构具有多个串联的存储器子阵列（其包括至少一个存储器单元），连接到每个子阵列的匹配线，有效存储器单元，比较器接收 来自匹配线和有效存储器单元的输入，来自比较器的漏线输出和预充电器件。 取决于输入数据与存储装置中的数据的比较操作的结果，汇流线和匹配线从第一电压复位到第二电压。 当匹配线上出现第二个电压，并且第一个电压出现在漏极线上时，这表示所有子阵列中的数据和输入数据之间的匹配。
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公开(公告)号：US06430072B1
公开(公告)日：2002-08-06
申请号：US09682638
申请日：2001-10-01
IPC分类号： G11C1500
摘要： A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.
摘要翻译： 一种用于内容可寻址存储器结构的方法和结构，其具有字的存储器阵列，每个字具有多个存储器位和多个匹配线。 每个匹配线连接到一个字，并且匹配线比较电路连接到匹配线，并且适于单独测试所有单词。 匹配线比较电路包括多个比较器，其数量与字数相等，使得每个字连接到专用比较器以允许单独测试存储器阵列中的每个字。
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公开(公告)号：US20080270962A1
公开(公告)日：2008-10-30
申请号：US12138871
申请日：2008-06-13
申请人： Thomas B. Chadwick , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wempie
发明人： Thomas B. Chadwick , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wempie
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。
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6.发明授权公开(公告)号：US06552920B2
公开(公告)日：2003-04-22
申请号：US09892396
申请日：2001-06-27
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.
摘要翻译： 用于改善内容可寻址存储器阵列的方法和结构具有多个串联的存储器子阵列（其包括至少一个存储器单元），连接到每个子阵列的匹配线，有效存储器单元，比较器接收 来自匹配线和有效存储器单元的输入，来自比较器的漏线输出和预充电器件。 取决于输入数据与存储装置中的数据的比较操作的结果，汇流线和匹配线从第一电压复位到第二电压。 当匹配线上出现第二个电压，并且第一个电压出现在漏极线上时，这表示所有子阵列中的数据和输入数据之间的匹配。
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