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1.发明授权公开(公告)号：US06711040B2
公开(公告)日：2004-03-23
申请号：US10353119
申请日：2003-01-28
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.
摘要翻译： 用于改善内容可寻址存储器阵列的方法和结构具有多个串联的存储器子阵列（其包括至少一个存储器单元），连接到每个子阵列的匹配线，有效存储器单元，比较器接收 来自匹配线和有效存储器单元的输入，来自比较器的漏线输出和预充电器件。 取决于输入数据与存储装置中的数据的比较操作的结果，汇流线和匹配线从第一电压复位到第二电压。 当匹配线上出现第二个电压，并且第一个电压出现在漏极线上时，这表示所有子阵列中的数据和输入数据之间的匹配。
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2.发明授权公开(公告)号：US06552920B2
公开(公告)日：2003-04-22
申请号：US09892396
申请日：2001-06-27
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.
摘要翻译： 用于改善内容可寻址存储器阵列的方法和结构具有多个串联的存储器子阵列（其包括至少一个存储器单元），连接到每个子阵列的匹配线，有效存储器单元，比较器接收 来自匹配线和有效存储器单元的输入，来自比较器的漏线输出和预充电器件。 取决于输入数据与存储装置中的数据的比较操作的结果，汇流线和匹配线从第一电压复位到第二电压。 当匹配线上出现第二个电压，并且第一个电压出现在漏极线上时，这表示所有子阵列中的数据和输入数据之间的匹配。
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公开(公告)号：US08595557B2
公开(公告)日：2013-11-26
申请号：US10906508
申请日：2005-02-23
IPC分类号： G06F11/00
CPC分类号： G11C29/12 , G11C29/56 , G11C2029/0405 , G11C2029/5604
摘要： A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.
摘要翻译： 公开了一种用于验证存储器测试软件的精度的方法。 内存自检（BIST）故障控制功能用于在存储器件的存储器阵列内的各个预定位置处产生多个模拟存储器故障。 然后，存储器阵列由存储器测试器测试。 之后，由存储器测试仪指示的所有存储器故障由逻辑到物理映射软件产生一个故障映射。 位故障映射提供由逻辑到物理映射软件导出的所有故障存储器位置。 然后将由逻辑到物理映射软件导出的故障存储器位置与预定的存储器位置进行比较，以验证逻辑到物理映射软件的准确性。
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公开(公告)号：US06426890B1
公开(公告)日：2002-07-30
申请号：US09770844
申请日：2001-01-26
申请人： Eric Jasinski , Douglas W. Kemerer
发明人： Eric Jasinski , Douglas W. Kemerer
IPC分类号： G11C1100
CPC分类号： G11C5/063 , G11C11/412
摘要： A memory cell layout provides for sharing of power supply connections between adjacent rows and columns of a memory array, respectively by providing a subarray layout in which one power connection is serpentine, extending into adjacent rows, and another stitches together a connection of memory cells in adjacent columns and adjacent rows. The subarray layout may be expanded by reflection and produced by lithographic exposures of relatively large numbers of memory cells in a step-and-repeat fashion. The layout of the power connections to the memory cells allows a significant reduction in the number of power connections required and/or the provision of redundant connections and a shielding mesh without increase of the number of connections required as well as full exploitation of minimum feature size with increased manufacturing yield.
摘要翻译： 存储单元布局分别通过提供一个子阵列布局来分配存储器阵列的相邻行和列之间的电源连接，其中一个电源连接是蛇形的，延伸到相邻的行中，并且另一个将存储器单元的连接在一起 相邻列和相邻行。 子阵列布局可以通过反射而扩展，并且以逐步重复的方式通过相对大量的存储器单元的光刻曝光产生。 与存储器单元的电力连接的布局允许显着减少所需的电力连接的数量和/或提供冗余连接和屏蔽网，而不需要增加所需的连接数量以及充分利用最小特征尺寸 增加制造产量。
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公开(公告)号：US20060190788A1
公开(公告)日：2006-08-24
申请号：US10906508
申请日：2005-02-23
申请人： Eric Jasinski , Michael Ouellette , Jeremy Rowland
发明人： Eric Jasinski , Michael Ouellette , Jeremy Rowland
IPC分类号： G01R31/28
CPC分类号： G11C29/12 , G11C29/56 , G11C2029/0405 , G11C2029/5604
摘要： A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.
摘要翻译： 公开了一种用于验证存储器测试软件的精度的方法。 内存自检（BIST）故障控制功能用于在存储器件的存储器阵列内的各个预定位置处产生多个模拟存储器故障。 然后，存储器阵列由存储器测试器测试。 之后，由存储器测试仪指示的所有存储器故障由逻辑到物理映射软件产生一个故障映射。 位故障映射提供由逻辑到物理映射软件导出的所有故障存储器位置。 然后将由逻辑到物理映射软件导出的故障存储器位置与预定的存储器位置进行比较，以验证逻辑到物理映射软件的准确性。
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