公开(公告)号：US20120216160A1

公开(公告)日：2012-08-23

申请号：US13365961

申请日：2012-02-03

申请人： Thomas Buechner ,  Markus Buehler ,  Philipp Panitz ,  Lei Wang ,  Markus Olbrich

发明人： Thomas Buechner ,  Markus Buehler ,  Philipp Panitz ,  Lei Wang ,  Markus Olbrich

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/78 ,  G06F2217/84

摘要： A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

摘要翻译： 一种方法包括估计电子​​电路的功耗。 估计包括基于用于全电路计算的电子电路的等级化结果将至少一个门的第一门分配到优先级队列中，并且将至少一个门的第二门分配到优先队列中，该优先队列中的扇出 栅极直接连接到调整大小的门的扇入栅极用于增量电路计算。 对于来自优先级队列的每个门，该估计包括执行以下操作。 通过静态时序分析和将毛刺窗口计算为差异来确定门的输出网络处的最新和最早的信号到达时间，并且基于毛刺窗口为输出网络计算转移度量。 这些操作包括确定信号转换的上限，以及基于上限来估计功耗。

公开(公告)号：US08407654B2

公开(公告)日：2013-03-26

申请号：US13365972

申请日：2012-02-03

申请人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

发明人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration.

摘要翻译： 一种方法包括降低电子电路的功耗，其中电子电路包括至少一个具有至少一个具有单个输出网的门的逻辑锥，其中至少一个门的表示是来自标准单元库的元件的实例。 降低功耗包括通过计算每个门的转换度量和功率度量来确定动态功耗的上限。 降低功耗包括选择具有大于预定阈值的功耗上限的门。 对于每个所选择的门，执行操作包括：通过针对所述多个配置中的每一个计算相应的功耗上限来测试来自所选择的门的标准单元库的多个配置; 选择门极配置，最小上限为功耗; 以及根据选择的门配置修改门级设计表示。

公开(公告)号：US08627263B2

公开(公告)日：2014-01-07

申请号：US13365989

申请日：2012-02-03

申请人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

发明人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/08

摘要： A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

摘要翻译： 一种方法包括从标准单元库确定门配置，以优化要调整大小的电子电路中的逻辑门的行为。 确定包括定义要调整大小的逻辑门的变量，并定义受逻辑门影响的网络以进行调整大小。 确定包括确定受到要调整大小的逻辑门影响的电子电路中的其他逻辑门的约束，并且制定目标函数。 该确定包括使用线性规划求解器基于所定义的变量和确定的约束求解目标函数。 确定包括输出由线性规划求解器获得的目标函数的解，用于进一步处理。 从标准单元库中选择栅极配置，以根据目标函数的求解来优化要调整大小的逻辑门的行为。

公开(公告)号：US08612911B2

公开(公告)日：2013-12-17

申请号：US13365961

申请日：2012-02-03

申请人： Thomas Buechner ,  Markus Buehler ,  Philipp Panitz ,  Lei Wang ,  Markus Olbrich

发明人： Thomas Buechner ,  Markus Buehler ,  Philipp Panitz ,  Lei Wang ,  Markus Olbrich

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/78 ,  G06F2217/84

摘要： A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

摘要翻译： 一种方法包括估计电子​​电路的功耗。 估计包括基于用于全电路计算的电子电路的等级化结果将至少一个门的第一门分配到优先级队列中，并且将至少一个门的第二门分配到优先队列中，该优先队列中的扇出 栅极直接连接到调整大小的门的扇入栅极用于增量电路计算。 对于来自优先级队列的每个门，该估计包括执行以下操作。 通过静态时序分析和将毛刺窗口计算为差异来确定门的输出网络处的最新和最早的信号到达时间，并且基于毛刺窗口为输出网络计算转移度量。 这些操作包括确定信号转换的上限，以及基于上限来估计功耗。

公开(公告)号：US20120266120A1

公开(公告)日：2012-10-18

申请号：US13365972

申请日：2012-02-03

申请人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

发明人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration.

摘要翻译： 一种方法包括降低电子电路的功耗，其中电子电路包括至少一个具有至少一个具有单个输出网的门的逻辑锥，其中至少一个门的表示是来自标准单元库的元件的实例。 降低功耗包括通过计算每个门的转换度量和功率度量来确定动态功耗的上限。 降低功耗包括选择具有大于预定阈值的功耗上限的门。 对于每个所选择的门，执行操作包括：通过针对所述多个配置中的每一个计算相应的功耗上限来测试来自所选择的门的标准单元库的多个配置; 选择门极配置，最小上限为功耗; 以及根据选择的门配置修改门级设计表示。

公开(公告)号：US20120216168A1

公开(公告)日：2012-08-23

申请号：US13365989

申请日：2012-02-03

申请人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

发明人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/08

摘要： A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function to be solved by the electronic circuit. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

摘要翻译： 一种方法包括从标准单元库确定门配置，以优化要调整大小的电子电路中的逻辑门的行为。 确定包括定义要调整大小的逻辑门的变量，并定义受逻辑门影响的网络以进行调整大小。 确定包括确定受到要调整的逻辑门影响的电子电路中的其他逻辑门的约束，并且制定由电子电路解决的目标函数。 该确定包括使用线性规划求解器基于所定义的变量和确定的约束求解目标函数。 确定包括输出由线性规划求解器获得的目标函数的解，用于进一步处理。 从标准单元库中选择栅极配置，以根据目标函数的求解来优化要调整大小的逻辑门的行为。

公开(公告)号：US08731858B2

公开(公告)日：2014-05-20

申请号：US12577920

申请日：2009-10-13

申请人： Markus Buehler ,  Juergen Kuehl ,  Markus Olbrich ,  Philipp Panitz

发明人： Markus Buehler ,  Juergen Kuehl ,  Markus Olbrich ,  Philipp Panitz

IPC分类号： G01R29/02 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Calculating a timing delay in a repeater network in an electronic circuit. The repeater network comprises a plurality of driving cells. At least one loop comprising one or more pins and one or more driving cells for driving the loop is implemented. Each driving cell in the loop is arranged between two branches of the loop. For each driving cell, the loop is opened a plurality of times per driving cell, with one open at a time. A dedicated arrival time of a signal at each sink of the repeater network for the one open at a time per driving cell is calculated. The dedicated arrival time is stored. The calculation step and the storing step is repeated until the dedicated arrival time at each sink of the repeater network is available for each of the opens per driving cell.

摘要翻译： 计算电子电路中继器网络中的定时延迟。 中继器网络包括多个驱动单元。 实现了包括一个或多个引脚和用于驱动回路的一个或多个驱动单元的至少一个回路。 环路中的每个驱动单元布置在环路的两个分支之间。 对于每个驱动单元，每个驱动单元打开多个循环，一次一个打开。 计算在每个驱动单元一次打开的中继器网络的每个宿处的信号的专用到达时间。 存储专用到达时间。 重复计算步骤和存储步骤，直到中继器网络的每个接收器的专用到达时间对于每个驱动单元的每个打开可用。

公开(公告)号：US20080059933A1

公开(公告)日：2008-03-06

申请号：US11845892

申请日：2007-08-28

申请人： Erich Barke ,  Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Panitz

发明人： Erich Barke ,  Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Panitz

IPC分类号： G06F17/50

CPC分类号： G06F17/509 ,  G06F17/5045 ,  G06F17/5077 ,  G06F2217/78 ,  G06F2217/84

摘要： The present invention relates to a method for designing fan-out nets connecting a signal source and a plurality of net elements in an integrated circuit. In order to make fan-out nets more robust against opens while keeping the risk due to short circuits in an acceptable degree, the method comprises the steps of: a) implementing a routing section in a closed structure comprising a plurality of signal receiving pins, wherein said receiving pins connect to further net elements, b) implementing on said closed structure a plurality of buffer elements to provide multiple signals derived from said source signal for driving said plurality of net elements, and c) limiting the distance and number of receiving cells between two buffer elements below predetermined values in order to keep a short circuit current given in case of an open tolerably small and within a worst case skew time delay.

摘要翻译： 本发明涉及一种在集成电路中设计连接信号源和多个网元的扇出网络的方法。 为了使扇出网络在打开的同时保持较强的鲁棒性，同时将短路的风险保持在可接受的程度，该方法包括以下步骤：a）实现包括多个信号接收引脚的封闭结构中的路由部分， 其中所述接收引脚连接到另外的网元件，b）在所述封闭结构上实现多个缓冲元件以提供从所述源信号导出的多个信号，用于驱动所述多个网元，以及c）限制接收单元的距离和数量 在两个缓冲元件之间低于预定值，以便在开路容许小的情况下以及在最坏情况下的扭曲时间延迟中保持短路电流。

公开(公告)号：US08015527B2

公开(公告)日：2011-09-06

申请号：US12166012

申请日：2008-07-01

申请人： Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Panitz

发明人： Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Panitz

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin and a receiving pin being coupled by at least one loop, the loop comprising a first branching path and a second branching path electrically parallel to the first branching path, wherein at least a first and a second branching point connect the branching paths. The method comprises the steps of disconnecting each branching path once at a time at a specific point in said the at least one loop which connects a driver to at least one specific receiving pin; calculating a delay value of a signal connection between the driver pin and each of the receiving pin for each of the disconnected branching paths of each loop; storing maximum and/or minimum calculated delay values; and applying at least one of the delay values for static timing analysis of the electronic circuit.

摘要翻译： 本发明涉及一种用于电子电路布线网的延迟计算方法，其中电子电路内的网包括一个驱动器引脚和一个由至少一个环耦合的接收引脚，该环包括第一分支路径和第二分支 所述路径电平行于所述第一分支路径，其中至少第一和第二分支点连接所述分支路径。 该方法包括以下步骤：在连接驱动器至少一个特定接收引脚的所述至少一个回路中的特定点处一次断开每个分支路径; 计算每个循环的每个断开的分支路径的驱动器引脚和每个接收引脚之间的信号连接的延迟值; 存储最大和/或最小计算的延迟值; 以及对电子电路的静态时序分析应用至少一个延迟值。

公开(公告)号：US20100100347A1

公开(公告)日：2010-04-22

申请号：US12577920

申请日：2009-10-13

申请人： Markus Buehler ,  Juergen Kuehl ,  Markus Olbrich ,  Philipp Panitz

发明人： Markus Buehler ,  Juergen Kuehl ,  Markus Olbrich ,  Philipp Panitz

IPC分类号： G01R29/02

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Calculating a timing delay in a repeater network in an electronic circuit. The repeater network comprises a plurality of driving cells. At least one loop comprising one or more pins and one or more driving cells for driving the loop is implemented. Each driving cell in the loop is arranged between two branches of the loop. For each driving cell, the loop is opened a plurality of times per driving cell, with one open at a time. A dedicated arrival time of a signal at each sink of the repeater network for the one open at a time per driving cell is calculated. The dedicated arrival time is stored. The calculation step and the storing step is repeated until the dedicated arrival time at each sink of the repeater network is available for each of the opens per driving cell.

摘要翻译： 计算电子电路中继器网络中的定时延迟。 中继器网络包括多个驱动单元。 实现了包括一个或多个引脚和用于驱动回路的一个或多个驱动单元的至少一个回路。 环路中的每个驱动单元布置在环路的两个分支之间。 对于每个驱动单元，每个驱动单元打开多个循环，一次一个打开。 计算在每个驱动单元一次打开的中继器网络的每个宿处的信号的专用到达时间。 存储专用到达时间。 重复计算步骤和存储步骤，直到中继器网络的每个接收器的专用到达时间对于每个驱动单元的每个打开可用。