公开(公告)号：US20060117233A1

公开(公告)日：2006-06-01

申请号：US10977922

申请日：2004-10-29

申请人： Thomas Cowell ,  Frank Ferriaolo ,  Kevin Gower ,  Frank LaPietra

发明人： Thomas Cowell ,  Frank Ferriaolo ,  Kevin Gower ,  Frank LaPietra

IPC分类号： G01R31/28

CPC分类号： G11C29/16 ,  G11C5/04 ,  G11C29/022 ,  G11C2029/4002

摘要： A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.

摘要翻译： 包括下游缓冲器，下游接收器，上游驱动器，上游接收器的缓冲存储器模块。 下游缓冲器和下游接收器都适于连接到分组级联互连存储器子系统中的下游存储器总线。 上游驱动器和上游接收器都适于连接到存储器子系统中的上游存储器总线。 在对存储器模块进行测试期间，上游驱动器连接到下游接收器，下游驱动器连接到上游接收器。 存储器模块还包括一个或多个存储寄存器，微处理器和服务接口端口。 微处理器包括用于执行存储器模块的测试的指令，包括将测试结果存储在存储寄存器中。 服务接口端口接收启动测试执行的服务接口信号，并访问存储寄存器以确定测试结果。

公开(公告)号：US20080065938A1

公开(公告)日：2008-03-13

申请号：US11937568

申请日：2007-11-09

申请人： Thomas Cowell ,  Frank Ferriaolo ,  Kevin Gower ,  Frank LaPietra

发明人： Thomas Cowell ,  Frank Ferriaolo ,  Kevin Gower ,  Frank LaPietra

IPC分类号： G11C29/08

CPC分类号： G11C29/16 ,  G11C5/04 ,  G11C29/022 ,  G11C2029/4002

摘要： A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.

摘要翻译： 缓冲存储器模块，包括下游缓冲器，下游接收器，上游驱动器，上游接收器。 下游缓冲器和下游接收器都适于连接到分组级联互连存储器子系统中的下游存储器总线。 上游驱动器和上游接收器都适于连接到存储器子系统中的上游存储器总线。 在对存储器模块进行测试期间，上游驱动器连接到下游接收器，下游驱动器连接到上游接收器。 存储器模块还包括一个或多个存储寄存器，微处理器和服务接口端口。 微处理器包括用于执行存储器模块的测试的指令，包括将测试结果存储在存储寄存器中。 服务接口端口接收启动测试执行的服务接口信号，并访问存储寄存器以确定测试结果。

公开(公告)号：US20060107186A1

公开(公告)日：2006-05-18

申请号：US10977790

申请日：2004-10-29

申请人： Thomas Cowell ,  Kevin Gower ,  Frank LaPietra

发明人： Thomas Cowell ,  Kevin Gower ,  Frank LaPietra

IPC分类号： H03M13/00

CPC分类号： G11C29/48 ,  G11C5/00 ,  G11C5/04 ,  G11C29/1201

摘要： A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.

公开(公告)号：US20080104290A1

公开(公告)日：2008-05-01

申请号：US11971578

申请日：2008-01-09

申请人： Thomas Cowell ,  Kevin Gower ,  Frank LaPietra

发明人： Thomas Cowell ,  Kevin Gower ,  Frank LaPietra

IPC分类号： G06F13/12

CPC分类号： G11C29/48 ,  G11C5/00 ,  G11C5/04 ,  G11C29/1201

摘要： A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.

摘要翻译： 用于测试存储器子系统的缓冲设备。 缓冲装置包括适于连接到低速总线的并行总线端口和适于连接到高速总线的串行总线端口。 高速总线以比慢速总线更快的速度运行。 缓冲装置还包括总线转换器，其具有用于将经由串行总线端口接收的串行分组化输入数据转换为并行总线输出数据的标准操作模式，以经由并行总线端口输出。 缓冲装置还包括用于将经由并行总线端口接收的并行总线输入数据转换为串行分组化输出数据以供经由串行总线端口输出的备用操作模式。 串行打包输入数据在串行打包输出数据的功能和时序上是一致的。