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1.发明授权Central processor supervised controller system having a simulation of the controller in the central processor for test purposes 失效中央处理器监督的控制器系统具有中央处理器中的控制器的模拟用于测试目的
公开(公告)号：US4385349A
公开(公告)日：1983-05-24
申请号：US208735
申请日：1980-11-20
IPC分类号： G06F11/22 , G05B19/4063 , G06F11/26 , G06F11/267 , G06F13/00 , G09B9/00 , G05B23/02 , G06F11/00
CPC分类号： G06F11/261 , G05B19/4063 , G05B2219/33285 , G05B2219/33286 , G05B2219/33324 , G05B2219/34466 , G06F11/2221
摘要： In a system for controlling a machine tool by a tool controller under the supervision of a central data processor, in which the controller transforms the data provided by the central processor into a format compatible with the machine tool, e.g., clock pulse encoded data format suitable for writing into and reading out of a serial storage magnetic memory device, a test system is provided wherein the central processor includes a simulation of the controller. This simulated controller gives the processor the capability of simulating and applying to the tool controller data in a format equivalent to that normally applied to the tool controller from the tool itself, e.g., a clock encoded data read output. The simulated controller also provides the central processor with the capability of receiving from the tool controller a tool control output in the format compatible with the control tool, e.g., clock encoded data and changing said data into an original format usable in the central processor.
摘要翻译： 在用于在中央数据处理器的监督下由工具控制器控制机床的系统中，其中控制器将由中央处理器提供的数据变换成与机床兼容的格式，例如适合于时钟脉冲编码的数据格式 为了写入和读出串行存储磁存储器件，提供了一种测试系统，其中中央处理器包括控制器的仿真。 该模拟控制器给予处理器以与工具控制器通常应用于工具本身的格式相当的格式来模拟和应用于工具控制器数据的能力，例如时钟编码数据读取输出。 模拟控制器还为中央处理器提供了以与控制工具兼容的格式（例如时钟编码数据）从工具控制器接收工具控制输出并将所述数据改变成可用于中央处理器的原始格式的能力。
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2.发明授权Safeguarding of data recorded on disk by tunnel erase magnetic head assembly 失效通过隧道擦除磁头组件保护磁盘上记录的数据
公开(公告)号：US4442463A
公开(公告)日：1984-04-10
申请号：US445123
申请日：1982-11-29
申请人： Rajan Krishnamurty , John A. Voltin
发明人： Rajan Krishnamurty , John A. Voltin
摘要： Apparatus is provided for the safeguarding of data recorded on disk and diskettes by tunnel erase magnetic head assembly which comprise a read/write transducer for magnetically recording data along tracks on said disk and a pair of magnetic erase transducers adjacent to the read/write transducer for limiting the width of the recorded data. The apparatus for safeguarding the recorded data comprises apparatus for sensing the activation of the erase and/or read/write transducer and apparatus responsive to such sensed activation for determining if the activation is erroneous.
摘要翻译： 提供了用于通过隧道擦除磁头组件保护记录在磁盘和磁盘上的数据的装置，其包括用于沿着所述磁盘上的磁道磁数据记录数据的读/写换能器和与读/写换能器相邻的一对磁擦除传感器， 限制记录数据的宽度。 用于保护记录数据的装置包括用于响应于这种感测到的激活来感测擦除和/或读/写换能器和装置的激活的装置，用于确定激活是否是错误的。
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公开(公告)号：US5068819A
公开(公告)日：1991-11-26
申请号：US647183
申请日：1991-01-24
IPC分类号： G06F15/78
CPC分类号： G06F15/8084
摘要： In a data processing system, a method for performing a series of operation sequence results and providing such results including the steps of (1) computing the results for each sequence of operations consecutively and (2) reading the results for the proceeding computations during the computation of a current operation result. This method further includes the use of registers for the temporary storage of the sequence results. During the computation of the operation sequence results, other registers are used in performing the sequence operations. The operations store parameters in a progressive fashion. In other words, the initial operations are performed in one set of registers while the final result from the sequence operation is stored in a different register. The result of a previous operation sequence computation is read from a register that is not being used during the computation of the current sequence operation. Also, included is an interlock capability to prevent the storing of sequence in registers that are concurrently being read.
摘要翻译： 在数据处理系统中，执行一系列操作序列结果并提供这样的结果的方法包括以下步骤：（1）连续地计算每个操作序列的结果;（2）在计算期间读取进行的计算结果 的当前操作结果。 该方法还包括使用寄存器来临时存储序列结果。 在运算序列结果的计算过程中，其他寄存器用于执行序列操作。 操作以渐进的方式存储参数。 换句话说，初始操作在一组寄存器中执行，而序列操作的最终结果存储在不同的寄存器中。 从计算当前顺序操作期间未使用的寄存器读取先前操作序列计算的结果。 另外，包括防止在同时被读取的寄存器中存储序列的互锁能力。
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公开(公告)号：US5386505A
公开(公告)日：1995-01-31
申请号：US161210
申请日：1993-11-30
摘要： Apparatus and methods for selectively controlling by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics video display system. A logic/multiplex control translates overlay and underlay data patterns from a multiple plane VRAM (Video Random Access Memory), referenced to the graphics system frame buffer, into window specific patterns. The window related translation is conveyed to conventional RAMDACs (Random Access Memory Digital-to-Analog Converters) for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamically written into a random access memory, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.
摘要翻译： 用于通过窗口选择性地控制图形视频显示系统中覆盖平面的数量，叠加调色板的数量以及覆盖/底层平面掩模的装置和方法。 逻辑/多路复用控制将参考图形系统帧缓冲器的多平面VRAM（视频随机存取存储器）的覆盖和底层数据模式转换为窗口特定模式。 窗口相关的翻译被传送到用于光栅扫描同步的数模转换的常规RAMDAC（随机存取存储器数模转换器）。 由控制器提供的转换响应于有选择地和动态地写入随机存取存储器中的数据，从而提供覆盖/底层数据到窗口不同和选择性覆盖/底层调色板功能的翻译。
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5.发明授权Processor controlled DMA controller for transferring instruction and data from memory to coprocessor 失效处理器控制的DMA控制器，用于将指令和数据从存储器传输到协处理器
公开(公告)号：US5001624A
公开(公告)日：1991-03-19
申请号：US303024
申请日：1989-01-25
CPC分类号： G06F13/28 , G06F13/385 , G06F11/2205
摘要： A data processing system including a processor that executes a plurality of instructions including at least one instruction that requires an external operation to be performed. The processor provides information for this external operation instruction to an external device and continues to execute instructions that do not require the results from this external operation. The external device receives the information from the processor, performs the external operation and provides the results to the processor. A further aspect of this data processing system is an interface that is interconnected between the processor and the external device. The processor provides the external operation information to the interface. The interface in turn provides the information to the external device and concurrently accesses data from the memory that will be required by the external device for performing the external operation.
摘要翻译： 一种数据处理系统，包括执行包括要执行外部操作的至少一个指令的多个指令的处理器。 处理器将外部操作指令的信息提供给外部设备，并继续执行不需要此外部操作的结果的指令。 外部设备从处理器接收信息，执行外部操作并将结果提供给处理器。 该数据处理系统的另一方面是在处理器和外部设备之间互连的接口。 处理器将外部操作信息提供给接口。 该接口又向外部设备提供信息，并且同时从存储器访问外部设备所需的用于执行外部操作的数据。
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