公开(公告)号：US5059897A

公开(公告)日：1991-10-22

申请号：US447328

申请日：1989-12-07

申请人： Thomas J. Aton ,  Satwinder Malhi ,  Masashi Hashimoto ,  Shivaling S. Mahant-Shitti ,  Oh-Kyong Kwon ,  Thirumalai Sridhar

发明人： Thomas J. Aton ,  Satwinder Malhi ,  Masashi Hashimoto ,  Shivaling S. Mahant-Shitti ,  Oh-Kyong Kwon ,  Thirumalai Sridhar

IPC分类号： G01R31/28 ,  H01L21/66

CPC分类号： G01R31/281

摘要： A system and method for testing the continuity of interconnecting nets on a substrate to be used in multi-chip technology is provided. The system includes coupling a test pad (15) to the net (12) to be tested. The test pad (15) is coupled through a diode (34) to a common node (32). The voltage of a first node (16) of the net (12) is sensed by a voltmeter (38) which is coupled to ground. A predetermined current signal is applied to each node (16, 18, 20, 22) in the net through the use of a probe (42). The voltage of the remaining nets (14) is sensed by a voltmeter (44). If an erroneous interconnection (31) is present between the net (12) to be tested and any other net (14) on the substrate, the voltage of the other net (14) will fluctuate. The voltmeter (38) will indicate if there is an electrical connection between the node (16) and the test pad (15) during testing. If an electrical path is established between each node in the net (12) and test pad (15), the continuity of the net (12) is established through the operation of Ohm's law.

摘要翻译： 提供了一种用于测试在多芯片技术中使用的基板上互连网络的连续性的系统和方法。 该系统包括将测试垫（15）耦合到要测试的网（12）。 测试焊盘（15）通过二极管（34）耦合到公共节点（32）。 网（12）的第一节点（16）的电压由耦合到地的电压计（38）感测。 通过使用探针（42）将预定电流信号施加到网中的每个节点（16,18,20,22）。 剩余网（14）的电压由电压计（44）感测。 如果要测试的网络（12）和基板上的任何其他网络（14）之间存在错误的互连（31），则另一个网络（14）的电压将波动。 电压表（38）将指示在测试期间节点（16）和测试垫（15）之间是否存在电气连接。 如果在网络（12）和测试板（15）中的每个节点之间建立电路径，则通过欧姆定律的操作建立网络（12）的连续性。

公开(公告)号：US5488613A

公开(公告)日：1996-01-30

申请号：US988383

申请日：1992-12-08

申请人： Thirumalai Sridhar

发明人： Thirumalai Sridhar

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318552

摘要： A scan path test architecture for testing circuits using multiple system clocks with different frequencies includes a controller (16) for disabling the system clocks during a test cycle and a master clock for generating a signal frequency signal to each circuit module (10a-c), eliminating the need for partitioning scan paths between modules and synchronizing system clocks.

摘要翻译： 用于测试使用具有不同频率的多个系统时钟的电路的扫描路径测试架构包括用于在测试周期期间禁用系统时钟的控制器（16）和用于向每个电路模块（10a-c）生成信号频率信号的主时钟， 无需分区模块之间的扫描路径和同步系统时钟。

公开(公告)号：US4597080A

公开(公告)日：1986-06-24

申请号：US551648

申请日：1983-11-14

申请人： Satish M. Thatte ,  Thirumalai Sridhar ,  David S. Ho ,  Han-Tzong Yuan ,  Theo J. Powell

发明人： Satish M. Thatte ,  Thirumalai Sridhar ,  David S. Ho ,  Han-Tzong Yuan ,  Theo J. Powell

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318547

摘要： A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation of a functional test coupled with the data monitor are used for an off-line self-test of the data path in field. The control monitor is used to decouple the testing task of the control section from that of the data path.

摘要翻译： 使用位分层面向总线的数据路径来测试VLSI处理器的方法和装置包括用于片上存储器的数据和控制监视器以及BIT。 数据监视器用于压缩由数据路径产生的输出数据。 使用与数据监视器相结合的功能测试的BIT实现用于现场数据路径的离线自检。 控制监视器用于将控制部分的测试任务与数据通路的测试任务分离。

公开(公告)号：US4601034A

公开(公告)日：1986-07-15

申请号：US595065

申请日：1984-03-30

申请人： Thirumalai Sridhar

发明人： Thirumalai Sridhar

IPC分类号： G11C29/12 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/40

CPC分类号： G01R31/318547 ,  G11C29/40

摘要： Apparatus for testing high density VLSI memory elements of a semiconductor chip having bit line connections to at least selected ones of which includes a parallel signature analyzer built onto the chip adjacent the memory elements and connected to at least some of them by the bit line connections. The parallel signature analyzer is configurable to apply selected signals onto the bit lines in one mode to enable test signals to be written into selected memory cells to generate preselected memory states therewithin. The parallel signature analyzer is also configurable, in another mode to read the states of the memory cells and to develop a signature of the states read to indicate whether the selectively applied signals were properly written into and read from the high density memory. Means are also provided for delivering the signature to an output lead in the form of a quotient bit, if desired.

摘要翻译： 用于测试半导体芯片的高密度VLSI存储器元件的装置，其具有至少选定的位线连接的至少一个选择的半导体芯片，其包括构建在与所述存储器元件相邻的所述芯片上的并行签名分析器，并且通 并行签名分析器可配置为以一种模式将选定信号施加到位线上，以使测试信号能够写入所选择的存储单元以在其中产生预先选择的存储器状态。 并行签名分析器也是可配置的，在另一种模式下，读取存储器单元的状态并且开发读取的状态的签名，以指示选择性地施加的信号是否被适当地写入高密度存储器并从其读取。 如果需要，还提供了用于将商标以商位形式传送到输出引线的手段。