摘要:
A serial interface bus system for transmitting and receiving a plurality of bus signals which collectively allow communication of data between a digital audio source (12, 22, 24, 26, 56, 82) such as a compact disc and a digital sink (42, 52, 62, 64, 66) such as a digital signal processor. The plurality of bus signals provided by the interface bus system allow many different audio sources and sinks to be used without glue logic. The plurality of bus signals allow multiple transceivers to be configured in a daisy chain (20, 60) wherein a master is selectively chosen to optimize performance of such a system. The daisy chain configuration may be implemented to provide digital data to a wide variety of storage circuits for digital information.
摘要:
A phase lock loop circuit (10) which locks to a frequency within a range of input signal frequencies. A frequency discriminator (12) of phase lock loop circuit (10) determines a maximum pulse width of the input signal by counting a number of pulses of a reference signal in each of a series of pulses of the input signal. A coarse frequency controller (16) compares the maximum pulse width to two threshold values to determine whether the reference signal should be coarsely or finely adjusted. If the reference signal is coarsely adjusted, control circuit (16) provides a coarse frequency control signal to indicate whether a voltage controlled oscillator, VCO, (26) should increase or decrease the reference frequency. If the reference frequency is finely adjusted, a phase discriminator (22) provides a fine frequency control signal to the VCO to either increase or decrease the frequency of the reference signal with greater resolution.
摘要:
An interface transceiver (16) circuit and method for communicating transceiver control and status information between a signal processor (20) and either an audio source (12) or an audio sink (24). During transmission of digital audio data from audio source (12) and signal processor (20), a comparator (49) compares a cyclic redundancy check (CRCC) byte of a block of channel status information to a theoretical CRCC byte generated by a CRC generator (48). By comparing actual and theoretical CRCC bytes, comparator (49) indicates in a single bit whether audio data was transmitted correctly. Remaining bits of the CRCC byte are then used to transfer status information corresponding to transceiver (16). Similarly, during transmission of digital data from signal processor (20) to audio sink (24), a parity bit of a subframe of the digital data is used to transfer programming information from signal processor (20) to audio sink (24).