Serial interface bus system for transmitting and receiving digital audio
information
    1.
    发明授权
    Serial interface bus system for transmitting and receiving digital audio information 失效
    用于发送和接收数字音频信息的串行接口总线系统

    公开(公告)号:US5359626A

    公开(公告)日:1994-10-25

    申请号:US939770

    申请日:1992-09-02

    IPC分类号: G11B20/10 H04B1/20 H04B1/38

    CPC分类号: H04B1/205 G11B20/10527

    摘要: A serial interface bus system for transmitting and receiving a plurality of bus signals which collectively allow communication of data between a digital audio source (12, 22, 24, 26, 56, 82) such as a compact disc and a digital sink (42, 52, 62, 64, 66) such as a digital signal processor. The plurality of bus signals provided by the interface bus system allow many different audio sources and sinks to be used without glue logic. The plurality of bus signals allow multiple transceivers to be configured in a daisy chain (20, 60) wherein a master is selectively chosen to optimize performance of such a system. The daisy chain configuration may be implemented to provide digital data to a wide variety of storage circuits for digital information.

    摘要翻译: 一种串行接口总线系统,用于发送和接收多个总线信号,这些总线信号共同允许诸如光盘的数字音频源(12,22,24,26,56,82)与数字接收器(42)之间的数据通信, 52,62,64,66),例如数字信号处理器。 由接口总线系统提供的多个总线信号允许在没有胶合逻辑的情况下使用许多不同的音频源和接收器。 多个总线信号允许将多个收发器配置在菊花链(20,60)中,其中选择性地选择主机以优化这种系统的性能。 可以实现菊花链配置以将数字数据提供给用于数字信息的各种存储电路。

    Phase lock loop frequency correction circuit
    2.
    发明授权
    Phase lock loop frequency correction circuit 失效
    锁相环频率校正电路

    公开(公告)号:US5278874A

    公开(公告)日:1994-01-11

    申请号:US939745

    申请日:1992-09-02

    CPC分类号: H03L7/113 H04L7/06 H04L7/10

    摘要: A phase lock loop circuit (10) which locks to a frequency within a range of input signal frequencies. A frequency discriminator (12) of phase lock loop circuit (10) determines a maximum pulse width of the input signal by counting a number of pulses of a reference signal in each of a series of pulses of the input signal. A coarse frequency controller (16) compares the maximum pulse width to two threshold values to determine whether the reference signal should be coarsely or finely adjusted. If the reference signal is coarsely adjusted, control circuit (16) provides a coarse frequency control signal to indicate whether a voltage controlled oscillator, VCO, (26) should increase or decrease the reference frequency. If the reference frequency is finely adjusted, a phase discriminator (22) provides a fine frequency control signal to the VCO to either increase or decrease the frequency of the reference signal with greater resolution.

    摘要翻译: 锁相环电路(10),其锁定在输入信号频率范围内的频率。 锁相环电路(10)的鉴频器(12)通过对输入信号的一系列脉冲中的每一个中的参考信号的脉冲数进行计数来确定输入信号的最大脉冲宽度。 粗频率控制器(16)将最大脉冲宽度与两个阈值进行比较,以确定参考信号是粗略地还是微调。 如果参考信号被粗调,则控制电路(16)提供粗略的频率控制信号,以指示压控振荡器VCO(26)是否应增加或减少参考频率。 如果参考频率被精细调整,则相位鉴别器(22)向VCO提供精细的频率控制信号,以增加或降低具有更高分辨率的参考信号的频率。

    Circuit and method for receiving and transmitting control and status
information
    3.
    发明授权
    Circuit and method for receiving and transmitting control and status information 失效
    用于接收和发送控制和状态信息的电路和方法

    公开(公告)号:US5258999A

    公开(公告)日:1993-11-02

    申请号:US770507

    申请日:1991-10-03

    CPC分类号: H04L1/0061 G06F1/22 H04B1/207

    摘要: An interface transceiver (16) circuit and method for communicating transceiver control and status information between a signal processor (20) and either an audio source (12) or an audio sink (24). During transmission of digital audio data from audio source (12) and signal processor (20), a comparator (49) compares a cyclic redundancy check (CRCC) byte of a block of channel status information to a theoretical CRCC byte generated by a CRC generator (48). By comparing actual and theoretical CRCC bytes, comparator (49) indicates in a single bit whether audio data was transmitted correctly. Remaining bits of the CRCC byte are then used to transfer status information corresponding to transceiver (16). Similarly, during transmission of digital data from signal processor (20) to audio sink (24), a parity bit of a subframe of the digital data is used to transfer programming information from signal processor (20) to audio sink (24).

    摘要翻译: 一种用于在信号处理器(20)和音频源(12)或音频接收器(24)之间传送收发器控制和状态信息的接口收发器(16)电路和方法。 在从音频源(12)和信号处理器(20)传输数字音频数据期间,比较器(49)将信道状态信息块的循环冗余校验(CRCC)字节与CRC发生器产生的理论CRCC字节进行比较 (48)。 通过比较实际和理论CRCC字节,比较器(49)在单个位中指示音频数据是否被正确传输。 然后使用CRCC字节的剩余比特来传送对应于收发信机(16)的状态信息。 类似地,在将数字数据从信号处理器(20)传输到音频宿(24)期间,数字数据的子帧的奇偶校验位用于将编程信息从信号处理器(20)传送到音频宿(24)。