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    APPARATUS, METHOD AND PROGRAM PRODUCT FOR INITIATING COMPUTER SYSTEM OPERATION
    5.
    发明申请
    APPARATUS, METHOD AND PROGRAM PRODUCT FOR INITIATING COMPUTER SYSTEM OPERATION 有权
    用于启动计算机系统运行的装置，方法和程序产品

    公开(公告)号：US20080282077A1

    公开(公告)日：2008-11-13

    申请号：US11939826

    申请日：2007-11-14

    申请人： Seiichi Kawano ,  Kenneth Blair Ocheltree ,  Robert Stephen Olyha, JR.

    发明人： Seiichi Kawano ,  Kenneth Blair Ocheltree ,  Robert Stephen Olyha, JR.

    IPC分类号： G06F9/00

    CPC分类号： G06F1/24

    摘要： A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

    摘要翻译： 一种计算机系统，包括用于通过程序控制执行各种处理的CPU和存储至少一个操作系统和BIOS的存储元件，其中在启动系统时，CPU识别系统自己的硬件配置，并启动所选择的一个操作系统 根据在BIOS的控制下的识别的硬件配置存储在存储元件中。

    System and method for self-identifying and configuring the nodes of a network
    7.
    发明授权
    System and method for self-identifying and configuring the nodes of a network 失效
    用于自我识别和配置网络节点的系统和方法

    公开(公告)号：US06188675B1

    公开(公告)日：2001-02-13

    申请号：US08702778

    申请日：1996-08-23

    申请人： Daniel Francis Casper ,  Thomas Anthony Gregg ,  George Wayne Nation ,  Kenneth Blair Ocheltree ,  Charles Bertram Perkins, Jr.

    发明人： Daniel Francis Casper ,  Thomas Anthony Gregg ,  George Wayne Nation ,  Kenneth Blair Ocheltree ,  Charles Bertram Perkins, Jr.

    IPC分类号： H04L1228

    CPC分类号： H04L45/02 ,  H04L45/26

    摘要： A system and method for progressively identifying and configuring the nodes of a network having an unknown or partially unknown topology are presented. A special all-node address indicator is designated for insertion in a packet to be sent from a given node with known node address to a next adjacent node with unknown node address. Each node contains a port control register for each port of the node which when set instructs the node to insert the all-node address indicator into a packet to be forwarded to a next adjacent node in the network with unknown node address. The port control registers are remotely selectively set by one or more managing nodes of the network. Race condition is avoided by provision of a set count register associated with an address node register and managing node address register within each node of the network. A node can be configured only if the previously read set count value remains unchanged between reading of and writing to the address node register or managing node address register. Provision for identifying additions, deletions and other changes to the network automatically is also provided.

    摘要翻译： 提出了用于逐渐识别和配置具有未知或部分未知拓扑的网络的节点的系统和方法。 指定特殊的全节点地址指示符用于插入到具有已知节点地址的给定节点发送到具有未知节点地址的下一个相邻节点的分组中。 每个节点包含一个端口控制寄存器，用于节点的每个端口，当设置时指示节点将全节点地址指示符插入到要转发到具有未知节点地址的网络中的下一个相邻节点的数据包中。 端口控制寄存器由网络的一个或多个管理节点进行远程选择性设置。 通过提供与地址节点寄存器相关联的设置计数寄存器和管理网络的每个节点内的节点地址寄存器来避免竞争条件。 只有在先前读取的设置计数值在读取和写入地址节点寄存器或管理节点地址寄存器之间保持不变时才能配置节点。 还提供了自动识别网络添加，删除和其他更改的规定。

    Apparatus, method and program product for initiating computer system operation
    8.
    发明授权
    Apparatus, method and program product for initiating computer system operation 有权
    用于启动计算机系统操作的装置，方法和程序产品

    公开(公告)号：US07945772B2

    公开(公告)日：2011-05-17

    申请号：US12648728

    申请日：2009-12-29

    申请人： Seiichi Kawano ,  Kenneth Blair Ocheltree ,  Robert Stephen Olyha, Jr.

    发明人： Seiichi Kawano ,  Kenneth Blair Ocheltree ,  Robert Stephen Olyha, Jr.

    IPC分类号： G06F9/00 ,  G06F15/177

    CPC分类号： G06F1/24

    摘要： A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

    摘要翻译： 一种计算机系统，包括用于通过程序控制执行各种处理的CPU和存储至少一个操作系统和BIOS的存储元件，其中在启动系统时，CPU识别系统自己的硬件配置，并启动所选择的一个操作系统 根据在BIOS的控制下的识别的硬件配置存储在存储元件中。

    APPARATUS, METHOD AND PROGRAM PRODUCT FOR INITIATING COMPUTER SYSTEM OPERATION
    9.
    发明申请
    APPARATUS, METHOD AND PROGRAM PRODUCT FOR INITIATING COMPUTER SYSTEM OPERATION 有权
    用于启动计算机系统运行的装置，方法和程序产品

    公开(公告)号：US20100106952A1

    公开(公告)日：2010-04-29

    申请号：US12648728

    申请日：2009-12-29

    申请人： Seiichi Kawano ,  Kenneth Blair Ocheltree ,  Robert Stephen Olyha, JR.

    发明人： Seiichi Kawano ,  Kenneth Blair Ocheltree ,  Robert Stephen Olyha, JR.

    IPC分类号： G06F1/32 ,  G06F9/24

    CPC分类号： G06F1/24

    摘要： A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

    摘要翻译： 一种计算机系统，包括用于通过程序控制执行各种处理的CPU和存储至少一个操作系统和BIOS的存储元件，其中在启动系统时，CPU识别系统自己的硬件配置，并启动所选择的一个操作系统 根据在BIOS的控制下的识别的硬件配置存储在存储元件中。

    System and method for maintaining cache coherency using path directories
    10.
    发明授权
    System and method for maintaining cache coherency using path directories 失效
    使用路径目录维护高速缓存一致性的系统和方法

    公开(公告)号：US5900015A

    公开(公告)日：1999-05-04

    申请号：US694894

    申请日：1996-08-09

    申请人： Lorraine Maria Paola Herger ,  Kwok-Ken Mak ,  Kenneth Blair Ocheltree ,  Tu-Chih Tsai ,  Michael Edward Wazlowski

    发明人： Lorraine Maria Paola Herger ,  Kwok-Ken Mak ,  Kenneth Blair Ocheltree ,  Tu-Chih Tsai ,  Michael Edward Wazlowski

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0824 ,  G06F12/0813

    摘要： A method of maintaining cache coherency in a computer system including two or more processors sharing information, the processors coupled by two or more interconnects to a memory such that the processors are not directly coupled to the same is disclosed interconnect is disclosed. The method of maintaining cache coherency includes the steps of: accessing and sharing, by a first processor and a second processor, information from the memory and setting path indicators in directories associated with at least two of the interconnects on a respective first and second access path to the memory, and storing the information in respective associated first and second caches; and writing a new value to the information, by a writing processor sharing the information, the writing step including the steps of: invalidating other copies of the information via the path indicators; acquiring exclusive access to the information by changing the path indicators to an exclusive state; and writing the new value to the information, in response to the acquiring step.

    摘要翻译： 公开了一种在包括共享信息的两个或多个处理器共享信息的计算机系统中维持高速缓存一致性的方法，将两个或多个互连器耦合到存储器，使得处理器不直接耦合到存储器的处理器。 维护高速缓存一致性的方法包括以下步骤：由第一处理器和第二处理器访问和共享来自存储器的信息，并且在相应的第一和第二访问路径上与至少两个互连相关联的目录中设置路径指示符 并将信息存储在相关联的第一和第二高速缓存中; 并且通过共享所述信息的写入处理器向所述信息写入新的值，所述写入步骤包括以下步骤：通过所述路径指示器使所述信息的其他副本无效; 通过将路径指示器更改为独占状态来获取对信息的独占访问; 并且响应于获取步骤将新的值写入信息。