公开(公告)号：US09398533B2

公开(公告)日：2016-07-19

申请号：US13287637

申请日：2011-11-02

申请人： Tilo Ferchland ,  Sascha Beyer ,  Michael Schmidt

发明人： Tilo Ferchland ,  Sascha Beyer ,  Michael Schmidt

IPC分类号： H04W52/02 ,  H04W28/22 ,  H04W84/10 ,  H04W92/18 ,  H04W4/00 ,  H04W56/00

CPC分类号： H04W52/0229 ,  H04W4/00 ,  H04W28/22 ,  H04W56/00 ,  H04W84/10 ,  H04W92/18 ,  Y02D70/142 ,  Y02D70/144

摘要： In one embodiment, setting, by a first node, a settable data rate for a first part of a data frame, the data frame also having a second part having a defined second data rate, and transmitting, by the node, the first part at the set data rate and the second part at the second data rate, the first part including at least a portion of a payload of the data frame and the second part including an identifier based on the set data rate.

摘要翻译： 在一个实施例中，由第一节点设置数据帧的第一部分的可设置数据速率，数据帧还具有具有定义的第二数据速率的第二部分，并且由节点将第一部分发送到 所述设置数据速率和所述第二部分处于所述第二数据速率，所述第一部分包括所述数据帧的有效载荷的至少一部分，并且所述第二部分包括基于所设置的数据速率的标识符。

公开(公告)号：US20120106529A1

公开(公告)日：2012-05-03

申请号：US13287637

申请日：2011-11-02

申请人： Tilo Ferchland ,  Sascha Beyer ,  Michael Schmidt

发明人： Tilo Ferchland ,  Sascha Beyer ,  Michael Schmidt

IPC分类号： H04W4/00 ,  H04W56/00

CPC分类号： H04W52/0229 ,  H04W4/00 ,  H04W28/22 ,  H04W56/00 ,  H04W84/10 ,  H04W92/18 ,  Y02D70/142 ,  Y02D70/144

摘要： In one embodiment, setting, by a first node, a settable data rate for a first part of a data frame, the data frame also having a second part having a defined second data rate, and transmitting, by the node, the first part at the set data rate and the second part at the second data rate, the first part including at least a portion of a payload of the data frame and the second part including an identifier based on the set data rate.

摘要翻译： 在一个实施例中，由第一节点设置数据帧的第一部分的可设置数据速率，数据帧还具有具有定义的第二数据速率的第二部分，并且由节点将第一部分发送到 所述设置数据速率和所述第二部分处于所述第二数据速率，所述第一部分包括所述数据帧的有效载荷的至少一部分，并且所述第二部分包括基于所设置的数据速率的标识符。

公开(公告)号：US07859435B2

公开(公告)日：2010-12-28

申请号：US12580826

申请日：2009-10-16

申请人： Tilo Ferchland ,  Eric Sachse ,  Michael Schmidt

发明人： Tilo Ferchland ,  Eric Sachse ,  Michael Schmidt

IPC分类号： H03M7/00

CPC分类号： H03H17/0685 ,  H03H17/0275

摘要： A method for a rate increase and a method for a rate reduction of a sampling input sequence into a sampling output sequence is provided. The sampling input sequence is subjected to signal processing. Signal processing maps a spreading with a first factor and an interpolation and a decimation with a second factor to generate the sampling output sequence with use of a counter. The counter and the signal processing are clocked with the higher rate, in each case, of the sampling input sequence or the sampling output sequence, respectively.

摘要翻译： 提供了一种用于速率增加的方法和用于将采样输入序列降低为采样输出序列的方法。 采样输入序列经过信号处理。 信号处理利用第一因子和内插和具有第二因子的抽取来映射扩展，以使用计数器生成采样输出序列。 计数器和信号处理分别以采样输入序列或采样输出序列的每种情况下的较高速率计时。

公开(公告)号：US20100103000A1

公开(公告)日：2010-04-29

申请号：US12580826

申请日：2009-10-16

申请人： Tilo FERCHLAND ,  Eric Sachse ,  Michael Schmidt

发明人： Tilo FERCHLAND ,  Eric Sachse ,  Michael Schmidt

IPC分类号： H03M7/00

CPC分类号： H03H17/0685 ,  H03H17/0275

摘要： A method for a rate increase and a method for a rate reduction of a sampling input sequence into a sampling output sequence is provided. The sampling input sequence is subjected to signal processing. Signal processing maps a spreading with a first factor and an interpolation and a decimation with a second factor to generate the sampling output sequence with use of a counter. The counter and the signal processing are clocked with the higher rate, in each case, of the sampling input sequence or the sampling output sequence, respectively.

摘要翻译： 提供了一种用于速率增加的方法和用于将采样输入序列降低为采样输出序列的方法。 采样输入序列经过信号处理。 信号处理利用第一因子和内插和具有第二因子的抽取来映射扩展，以使用计数器生成采样输出序列。 计数器和信号处理分别以采样输入序列或采样输出序列的每种情况下的较高速率计时。

公开(公告)号：US09239370B2

公开(公告)日：2016-01-19

申请号：US12824874

申请日：2010-06-28

申请人： Tilo Ferchland ,  Michael Schmidt ,  Eric Sachse

发明人： Tilo Ferchland ,  Michael Schmidt ,  Eric Sachse

IPC分类号： H04L1/16 ,  G01S5/02 ,  H04J3/06 ,  H04L1/18 ,  H04L1/20 ,  H04W56/00 ,  G01S13/76

CPC分类号： H04W4/02 ,  G01S5/0289 ,  G01S13/765 ,  H04J3/0682 ,  H04L1/1848 ,  H04L1/188 ,  H04L1/205 ,  H04W56/0055 ,  H04W56/0065

摘要： A circuit of a node in a radio network and method for transit time measurement between a first node and a second node of a radio network is provided. A frame is transmitted by the first node, wherein the frame requires an acknowledgment of reception by the second node. A first point in time of the transmission of the frame is established by the first node by a time counter. The frame is received by the second node at a second point in time. The acknowledgment is transmitted by the second node to the first node at a third point in time, wherein the third point in time depends on the second point in time by a predetermined time interval between the second point in time and the third point in time. A fourth point in time is established by the first node by the time counter when the acknowledgment is received. The transit time or the change in transit time is determined from the first point in time established by the time counter and from the established fourth point in time and from the predetermined time interval.

摘要翻译： 提供无线电网络中的节点的电路和无线电网络的第一节点和第二节点之间的传输时间测量方法。 帧由第一节点发送，其中帧需要由第二节点接收的确认。 帧的发送的第一时间点由第一节点通过时间计数器建立。 帧在第二时间点由第二节点接收。 所述确认在第三时间点由所述第二节点发送到所述第一节点，其中所述第三时间点在所述第二时间点上依赖于所述第二时间点在所述第二时间点和所述第三时间点之间的预定时间间隔。 当接收到确认时，由第一节点通过时间计数器建立第四时间点。 从通过时间计数器建立的第一时间点和从建立的第四时间点到预定的时间间隔确定通行时间或通行时间的变化。

公开(公告)号：US20120045016A1

公开(公告)日：2012-02-23

申请号：US13285998

申请日：2011-10-31

申请人： Michael Schmidt ,  Frank Poegel ,  Tilo Ferchland

发明人： Michael Schmidt ,  Frank Poegel ,  Tilo Ferchland

IPC分类号： H04L27/00

CPC分类号： H04J13/16 ,  H04B1/707

摘要： A transmission circuit and method for transmitting a bit sequence to be transmitted is provided that includes a dividing device for dividing the bit sequence into an even-numbered bit sequence and into an odd-numbered bit sequence, a first device for forming the first sampled values of a first fundamental wave depending on the even-numbered bit sequence, a second device for forming second sampled values of a second fundamental wave depending on the odd-numbered bit sequence, the second fundamental wave being shifted relative to the first fundamental wave by a time period, and includes a summator for summation of the first sampled values of the first fundamental wave and the second sampled values of the second fundamental wave to form an output value sequence.

摘要翻译： 提供一种用于发送要发送的比特序列的发送电路和方法，其包括用于将比特序列分割为偶数比特序列和奇数比特序列的分割装置，用于形成第一采样值的第一装置 取决于偶数比特序列的第一基波的第二装置，用于根据奇数比特序列形成第二基波的第二采样值的第二装置，第二基波相对于第一基波偏移一个 并且包括用于求和第一基波的第一采样值和第二基波的第二采样值的求和器，以形成输出值序列。

公开(公告)号：US08050295B2

公开(公告)日：2011-11-01

申请号：US12481269

申请日：2009-06-09

申请人： Michael Schmidt ,  Frank Poegel ,  Tilo Ferchland

发明人： Michael Schmidt ,  Frank Poegel ,  Tilo Ferchland

IPC分类号： H04L29/02

CPC分类号： H04J13/16 ,  H04B1/707

摘要： A transmission circuit and method for transmitting a bit sequence to be transmitted is provided that includes a dividing device for dividing the bit sequence into an even-numbered bit sequence and into an odd-numbered bit sequence, a first device for forming the first sampled values of a first fundamental wave depending on the even-numbered bit sequence, a second device for forming second sampled values of a second fundamental wave depending on the odd-numbered bit sequence, the second fundamental wave being shifted relative to the first fundamental wave by a time period, and includes a summator for summation of the first sampled values of the first fundamental wave and the second sampled values of the second fundamental wave to form an output value sequence.

摘要翻译： 提供一种用于发送要发送的比特序列的发送电路和方法，其包括用于将比特序列分割为偶数比特序列和奇数比特序列的分割装置，用于形成第一采样值的第一装置 取决于偶数比特序列的第一基波的第二装置，用于根据奇数比特序列形成第二基波的第二采样值的第二装置，第二基波相对于第一基波偏移一个 并且包括用于求和第一基波的第一采样值和第二基波的第二采样值的求和器，以形成输出值序列。

公开(公告)号：US08406117B2

公开(公告)日：2013-03-26

申请号：US13285998

申请日：2011-10-31

申请人： Michael Schmidt ,  Frank Poegel ,  Tilo Ferchland

发明人： Michael Schmidt ,  Frank Poegel ,  Tilo Ferchland

IPC分类号： H04J11/00

CPC分类号： H04J13/16 ,  H04B1/707

摘要： In certain embodiments, a circuitincludes a dividing device configured to divide a transmission bit sequence into a first bit sequence and a second bit sequence, bits adjacent to each other in the transmission bit sequence being separated by a bit time. The circuit includes a first device configured to generate first sampled values by sampling at a sampling rate a first fundamental wave that is based on the first bit sequence, and includes a second device configured to generate second sampled values by sampling at the sampling rate a second fundamental wave that is based on the second bit sequence, the second fundamental wave being shifted relative to the first fundamental wave by a time period. The circuit includes a summator configured to sum the first sampled values of the first fundamental wave and the second sampled values of the second fundamental wave to form an output value sequence.

摘要翻译： 在某些实施例中，电路包括被配置为将传输比特序列划分为第一比特序列和第二比特序列的分割装置，所述传输比特序列中彼此相邻的比特位被比特时间分隔。 该电路包括第一装置，其被配置为通过以采样率采样基于第一位序列的第一基波来产生第一采样值，并且包括第二装置，其被配置为通过以采样率采样第二采样值 基于第二比特序列的基波，第二基波相对于第一基波相移一段时间。 该电路包括一个加法器，其被配置为对第一基波的第一采样值和第二基波的第二采样值求和以形成输出值序列。

公开(公告)号：US20090304030A1

公开(公告)日：2009-12-10

申请号：US12481269

申请日：2009-06-09

申请人： Michael Schmidt ,  Frank Poegel ,  Tilo Ferchland

发明人： Michael Schmidt ,  Frank Poegel ,  Tilo Ferchland

IPC分类号： H04L29/02 ,  H04B14/04 ,  H04B1/69

CPC分类号： H04J13/16 ,  H04B1/707

摘要： A transmission circuit and method for transmitting a bit sequence to be transmitted is provided that includes a dividing device for dividing the bit sequence into an even-numbered bit sequence and into an odd-numbered bit sequence, a first device for forming the first sampled values of a first fundamental wave depending on the even-numbered bit sequence, a second device for forming second sampled values of a second fundamental wave depending on the odd-numbered bit sequence, the second fundamental wave being shifted relative to the first fundamental wave by a time period, and includes a summator for summation of the first sampled values of the first fundamental wave and the second sampled values of the second fundamental wave to form an output value sequence.

摘要翻译： 提供一种用于发送要发送的比特序列的发送电路和方法，其包括用于将比特序列分割为偶数比特序列和奇数比特序列的分割装置，用于形成第一采样值的第一装置 取决于偶数比特序列的第一基波的第二装置，用于根据奇数比特序列形成第二基波的第二采样值的第二装置，第二基波相对于第一基波偏移一个 并且包括用于求和第一基波的第一采样值和第二基波的第二采样值的求和器，以形成输出值序列。

公开(公告)号：US07058381B2

公开(公告)日：2006-06-06

申请号：US10361088

申请日：2003-02-07

申请人： Michael Schmidt ,  Wolfram Kluge ,  Tilo Ferchland

发明人： Michael Schmidt ,  Wolfram Kluge ,  Tilo Ferchland

IPC分类号： H04B1/10

CPC分类号： H04L25/03006 ,  H04B1/30

摘要： An equalizing device with notch compensation for a direct conversion receiver is disclosed. The baseband signal of a direct conversion receiver comprises a notch in the frequency response after the required DC compensation is performed. A bandpass generates a notch compensation signal on from a decision signal and a interference compensation signal of a decision feedback loop. Therefore, the reliability of the decision signal is enhanced and allows an improved data rate in WLAN applications.

摘要翻译： 公开了一种用于直接转换接收器的具有陷波补偿的均衡装置。 在执行所需的DC补偿之后，直接转换接收机的基带信号包括频率响应中的陷波。 带通从决策信号和决策反馈回路的干扰补偿信号产生一个陷波补偿信号。 因此，增强了决策信号的可靠性，并且允许在WLAN应用中提高数据速率。