公开(公告)号：US08681162B2

公开(公告)日：2014-03-25

申请号：US12905743

申请日：2010-10-15

申请人： Timour Paltashev ,  John Brothers ,  Yi-Jung Su ,  Yang (Jeff) Jiao

发明人： Timour Paltashev ,  John Brothers ,  Yi-Jung Su ,  Yang (Jeff) Jiao

IPC分类号： G06T1/00

CPC分类号： G06T15/005 ,  G06T9/00 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N19/82 ,  H04N19/86 ,  H04N19/91

摘要： A programmable graphics processing unit (GPU) includes a first shader stage configured to receive slice data from a frame buffer and perform variable length decoding (VLD), wherein the first shader stage outputs data to a first buffer within the frame buffer; a second shader stage configured to receive the output data from the first shader stage and perform transformation and motion compensation on the slice data, wherein the second shader stage outputs decoded slice data to a second buffer within the frame buffer; a third shader stage configured to receive the decoded slice data and perform in-loop deblocking filtering (IDF) on the frame buffer; a fourth shader stage configured to perform post-processing on the frame buffer; and a scheduler configured to schedule execution of the shader stages, the scheduler comprising a plurality of counter registers; wherein execution of the shader stages is synchronized utilizing the counter registers.

摘要翻译： 可编程图形处理单元（GPU）包括第一着色器级，其被配置为从帧缓冲器接收片数据并执行可变长度解码（VLD），其中第一着色器级将数据输出到帧缓冲器内的第一缓冲器; 第二着色器级，被配置为从所述第一着色器级接收所述输出数据，并对所述切片数据执行变换和运动补偿，其中所述第二着色器级将解码的切片数据输出到所述帧缓冲器内的第二缓冲器; 第三着色器级，被配置为接收所述解码的片数据并在所述帧缓冲器上执行循环去块滤波（IDF）; 第四着色器级，被配置为在所述帧缓冲器上执行后处理; 以及调度器，被配置为调度着色器级的执行，所述调度器包括多个计数器寄存器; 其中使用计数器寄存器来同步着色器级的执行。

公开(公告)号：US20120092353A1

公开(公告)日：2012-04-19

申请号：US12905743

申请日：2010-10-15

申请人： Timour Paltashev ,  John Brothers ,  Yi-Jung Su ,  Yang (Jeff) Jiao

发明人： Timour Paltashev ,  John Brothers ,  Yi-Jung Su ,  Yang (Jeff) Jiao

IPC分类号： H04N7/26 ,  G06T1/00

CPC分类号： G06T15/005 ,  G06T9/00 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N19/82 ,  H04N19/86 ,  H04N19/91

摘要： A multi-shader system in a programmable graphics processing unit (GPU) for processing video data, includes a first shader stage configured to receive slice data from a frame buffer and perform variable length decoding (VLD), wherein the first shader stage outputs data to a first buffer within the frame buffer; a second shader stage configured to receive the output data from the first shader stage and perform transformation and motion compensation on the slice data, wherein the second shader stage outputs decoded slice data to a second buffer within the frame buffer; a third shader stage configured to receive the decoded slice data and perform in-loop deblocking filtering (IDF) on the frame buffer; a fourth shader stage configured to perform post-processing on the frame buffer; and a scheduler configured to schedule execution of the shader stages, the scheduler comprising a plurality of counter registers; wherein execution of the shader stages is synchronized utilizing the counter registers.

摘要翻译： 用于处理视频数据的可编程图形处理单元（GPU）中的多着色器系统包括：第一着色器级，被配置为从帧缓冲器接收片数据并执行可变长度解码（VLD），其中第一着色器级将数据输出到 帧缓冲器内的第一缓冲器; 第二着色器级，被配置为从所述第一着色器级接收所述输出数据，并对所述切片数据执行变换和运动补偿，其中所述第二着色器级将解码的切片数据输出到所述帧缓冲器内的第二缓冲器; 第三着色器级，被配置为接收所述解码的片数据并在所述帧缓冲器上执行循环去块滤波（IDF）; 第四着色器级，被配置为在所述帧缓冲器上执行后处理; 以及调度器，被配置为调度着色器级的执行，所述调度器包括多个计数器寄存器; 其中使用计数器寄存器来同步着色器级的执行。

公开(公告)号：US07304897B2

公开(公告)日：2007-12-04

申请号：US10404425

申请日：2003-04-02

申请人： Chen-Kuan Eric Hong ,  Yi-Jung Su

发明人： Chen-Kuan Eric Hong ,  Yi-Jung Su

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G06F13/1684 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/105 ,  G11C2207/108

摘要： Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route a data strobe signal to a first number of the plurality of data channels for reading the data from the memory when the at least one multiplexer is in a first selected state, and wherein the at least one multiplexer is configured to route the data strobe signal to a second number of the plurality of data channels, wherein the second number is greater than the first number, for reading the data from the memory when the at least one multiplexer is in a second selected state. Such methods and systems may also comprise a clock for generating a data strobe signal, and a flip-flop for latching the data from the memory into the control circuit with the data strobe signal, wherein the data strobe signal does not leave the control circuit.

摘要翻译： 与本发明一致的方法和系统包括用于从包括多个数据通道的存储器读取数据的控制电路。 这样的控制电路包括至少一个多路复用器，其中至少一个多路复用器配置成将数据选通信号路由到多个数据通道的第一数目，以便当至少一个多路复用器处于第一 并且其中所述至少一个多路复用器被配置为将所述数据选通信号路由到所述多个数据信道的第二数目，其中所述第二数目大于所述第一数量，用于当所述第二数目在所述第一数量时从所述存储器读取数据， 至少一个多路复用器处于第二选择状态。 这样的方法和系统还可以包括用于产生数据选通信号的时钟，以及用于使用数据选通信号将来自存储器的数据锁存到控制电路中的触发器，其中数据选通信号不离开控制电路。

公开(公告)号：US07414900B2

公开(公告)日：2008-08-19

申请号：US11797306

申请日：2007-05-02

申请人： Chen-Kuan Eric Hong ,  Yi-Jung Su

发明人： Chen-Kuan Eric Hong ,  Yi-Jung Su

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G06F12/00 ,  G06F13/00 ,  H04L5/00 ,  H04L7/00

CPC分类号： G06F13/1684 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/105 ,  G11C2207/108

摘要： Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route a data strobe signal to a first number of the plurality of data channels for reading the data from the memory when the at least one multiplexer is in a first selected state, and wherein the at least one multiplexer is configured to route the data strobe signal to a second number of the plurality of data channels, wherein the second number is greater than the first number, for reading the data from the memory when the at least one multiplexer is in a second selected state. Such methods and systems may also comprise a clock for generating a data strobe signal, and a flip-flop for latching the data from the memory into the control circuit with the data strobe signal, wherein the data strobe signal does not leave the control circuit.

摘要翻译： 与本发明一致的方法和系统包括用于从包括多个数据通道的存储器读取数据的控制电路。 这样的控制电路包括至少一个多路复用器，其中至少一个多路复用器配置成将数据选通信号路由到多个数据通道的第一数目，以便当至少一个多路复用器处于第一 并且其中所述至少一个多路复用器被配置为将所述数据选通信号路由到所述多个数据信道的第二数目，其中所述第二数目大于所述第一数量，用于当所述第二数目在所述第一数量时从所述存储器读取数据， 至少一个多路复用器处于第二选择状态。 这样的方法和系统还可以包括用于产生数据选通信号的时钟，以及用于使用数据选通信号将来自存储器的数据锁存到控制电路中的触发器，其中数据选通信号不离开控制电路。

公开(公告)号：US20070237010A1

公开(公告)日：2007-10-11

申请号：US11797306

申请日：2007-05-02

申请人： Chen-Kuan Hong ,  Yi-Jung Su

发明人： Chen-Kuan Hong ,  Yi-Jung Su

IPC分类号： G11C7/22

CPC分类号： G06F13/1684 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/105 ,  G11C2207/108

摘要： Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route a data strobe signal to a first number of the plurality of data channels for reading the data from the memory when the at least one multiplexer is in a first selected state, and wherein the at least one multiplexer is configured to route the data strobe signal to a second number of the plurality of data channels, wherein the second number is greater than the first number, for reading the data from the memory when the at least one multiplexer is in a second selected state. Such methods and systems may also comprise a clock for generating a data strobe signal, and a flip-flop for latching the data from the memory into the control circuit with the data strobe signal, wherein the data strobe signal does not leave the control circuit.