公开(公告)号：US5970052A

公开(公告)日：1999-10-19

申请号：US933574

申请日：1997-09-19

申请人： Tin-Chee Lo ,  George A. Katopis ,  Timothy Gerard McNamara ,  David Allan Webber ,  Joseph L. Braun ,  Paul R. Turgeon

发明人： Tin-Chee Lo ,  George A. Katopis ,  Timothy Gerard McNamara ,  David Allan Webber ,  Joseph L. Braun ,  Paul R. Turgeon

IPC分类号： G01R31/3173 ,  G06F11/267

CPC分类号： G06F11/221 ,  G01R31/3173

摘要： A method for dynamic bandwidth testing of a link between two computer subsystems useful for determining the amount of data which can be buffered in a transmission line by delay, in which at each end of the line circuit modules are provided to couple the subsystem by a bi-directional multi-bit (BiDi) link, and providing within each said circuit module a built-in circuit and logic for dynamic transmission characterization and test of a said BiDi link between computer subsystems using built-in characterization logic macros, and during a test mode, switching said said built-in circuit and logic to test mode and using the test mode to characterize the link performance, and after the completion of characterization, the switching built-in characterization logic macros back to a normal system mode after programmatically setting timing parameters for the BiDi link to ensure safe operation of data transfer before the BiDi link is switched to system mode.

摘要翻译： 一种用于在两个计算机子系统之间的链路的动态带宽测试的方法，其用于确定可以通过延迟在传输线路中缓冲的数据量，其中在线路电路模块的每一端被提供以通过bi耦合子系统 并且在每个所述电路模块内提供内置电路和逻辑，用于使用内置的表征逻辑宏以及在测试期间对计算机子系统之间的所述BiDi链路进行动态传输表征和测试 模式，将所述内置电路和逻辑切换到测试模式并使用测试模式来表征链路性能，并且在表征完成之后，通过编程设置定时将交换内置表征逻辑宏恢复到正常的系统模式 BiDi链路的参数，以确保在BiDi链路切换到系统模式之前数据传输的安全运行。

公开(公告)号：US06205571B1

公开(公告)日：2001-03-20

申请号：US09222143

申请日：1998-12-29

申请人： Peter J. Camporese ,  Alina Deutsch ,  Timothy Gerard McNamara ,  Phillip John Restle ,  David Allan Webber

发明人： Peter J. Camporese ,  Alina Deutsch ,  Timothy Gerard McNamara ,  Phillip John Restle ,  David Allan Webber

IPC分类号： G06F1750

CPC分类号： G06F1/10 ,  G06F17/5077

摘要： An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of NSECTOR electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors. Each NSECTOR electrical net list is then tuned, wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of each NSECTOR electrical net list.

摘要翻译： 一个用于在VLSI芯片上分配时钟信号的X-Y网格树时钟分配网络。 可调式接线树网络与X-Y网格结合，垂直和水平连接所有树端点。 在X-Y网格的树端点的连接点不需要驱动程序。 最后的X-Y网格将时钟信号分配到每个需要的地方，并减少局部区域的偏差。 调谐方法允许缓冲时钟信号，同时最小化标称时钟偏移和时钟不确定度。 调谐树网络即使在时钟负载密度和非理想缓冲器放置的变化下也提供低偏移，同时最小化所需的缓冲器数量。 调谐方法首先表示作为集群电网负载的一个或多个时钟引脚负载和布线布线的总电容。 接下来，聚类网格负载的平滑近似于X-Y网格的效果。 为网络组件创建电气仿真模型，并且使用平滑的集群网格负载代替集群网格负载。 接下来通过提取具有相关联的X-Y网格线的网络列表来创建一组NSECTOR电网列表，以将每个扇区网络列表与其相邻扇区隔离。 然后调整每个NSECTOR电网列表，其中平滑的集群网格负载表示每个NSECTOR电网列表的相邻扇区的影响的近似值。

公开(公告)号：US06311313B1

公开(公告)日：2001-10-30

申请号：US09222141

申请日：1998-12-29

申请人： Peter J. Camporese ,  Alina Deutsch ,  Timothy Gerard McNamara ,  Phillip John Restle ,  David Allan Webber

发明人： Peter J. Camporese ,  Alina Deutsch ,  Timothy Gerard McNamara ,  Phillip John Restle ,  David Allan Webber

IPC分类号： G06F945

CPC分类号： G06F1/10

摘要： An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of NSECTOR electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors. Each NSECTOR electrical net list is then tuned, wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of each NSECTOR electrical net list.

摘要翻译： 一个用于在VLSI芯片上分配时钟信号的X-Y网格树时钟分配网络。 可调式接线树网络与X-Y网格结合，垂直和水平连接所有树端点。 在X-Y网格的树端点的连接点不需要驱动程序。 最后的X-Y网格将时钟信号分配到每个需要的地方，并减少局部区域的偏差。 调谐方法允许缓冲时钟信号，同时最小化标称时钟偏移和时钟不确定度。 调谐树网络即使在时钟负载密度和非理想缓冲器放置的变化下也提供低偏移，同时最小化所需的缓冲器数量。 调谐方法首先表示作为集群电网负载的一个或多个时钟引脚负载和布线布线的总电容。 接下来，聚类网格负载的平滑近似于X-Y网格的效果。 为网络组件创建电气仿真模型，并且使用平滑的集群网格负载代替集群网格负载。 接下来通过提取具有相关联的X-Y网格线的网络列表来创建一组NSECTOR电网列表，以将每个扇区网络列表与其相邻扇区隔离。 然后调整每个NSECTOR电网列表，其中平滑的集群网格负载表示每个NSECTOR电网列表的相邻扇区的影响的近似值。

公开(公告)号：US20080301411A1

公开(公告)日：2008-12-04

申请号：US12189797

申请日：2008-08-12

申请人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

发明人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F9/302 ,  G06F9/312

CPC分类号： G06F9/3001 ,  G06F9/3867

摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

摘要翻译： 一种通过使来自指令解码逻辑的控制信号反应在当前周期期间执行的操作的结果来操作算术逻辑单元（ALU）的方法，其指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。

公开(公告)号：US08024647B2

公开(公告)日：2011-09-20

申请号：US12047525

申请日：2008-03-13

申请人： Fadi Y. Busaba ,  Lawrence Joseph Powell ,  Martin Stanley Schmookler ,  Michael Thomas Vaden ,  David Allan Webber

发明人： Fadi Y. Busaba ,  Lawrence Joseph Powell ,  Martin Stanley Schmookler ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F11/10 ,  H03M13/00

CPC分类号： G06F11/2226

摘要： A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

摘要翻译： 公开了一种发现电路故障的方法。 该方法包括通过在操作数上执行所选功能来产生所选功能的第一结果，其中所选功能采用掩码。 一旦执行了该功能，就产生一个掩模的防范，并计算出锑的模数。 计算所选函数的第一结果的模函数以获得第三结果。 然后计算操作数的模以获得第四结果，然后对第二结果和第三结果执行第二函数以获得第五结果。 响应于将第五结果与第四结果进行比较，传播信号以指示电路中的故障。

公开(公告)号：US07509365B2

公开(公告)日：2009-03-24

申请号：US11056894

申请日：2005-02-11

申请人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

发明人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F7/38

CPC分类号： G06F9/3001 ,  G06F9/3867

摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

摘要翻译： 一种通过将当前周期内要执行的操作的结果与来自指令解码逻辑的控制信号相反的操作算术逻辑单元（ALU）的方法，该指令解码逻辑指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。

公开(公告)号：US07376890B2

公开(公告)日：2008-05-20

申请号：US10855734

申请日：2004-05-27

申请人： Fadi Y. Busaba ,  Lawrence Joseph Powell ,  Martin Stanley Schmookler ,  Michael Thomas Vaden ,  David Allan Webber

发明人： Fadi Y. Busaba ,  Lawrence Joseph Powell ,  Martin Stanley Schmookler ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F11/10

CPC分类号： G06F11/2226

摘要： A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

摘要翻译： 公开了一种发现电路故障的方法。 该方法包括通过在操作数上执行所选功能来产生所选功能的第一结果，其中所选功能采用掩码。 一旦执行了该功能，就产生一个掩模的防范，并计算出锑的模数。 计算所选函数的第一结果的模函数以获得第三结果。 然后计算操作数的模以获得第四结果，然后对第二结果和第三结果执行第二函数以获得第五结果。 响应于将第五结果与第四结果进行比较，传播信号以指示电路中的故障。

公开(公告)号：US07991816B2

公开(公告)日：2011-08-02

申请号：US12189797

申请日：2008-08-12

申请人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

发明人： Brian William Curran ,  Ashutosh Goyal ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F7/38

CPC分类号： G06F9/3001 ,  G06F9/3867

摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

摘要翻译： 一种通过将当前周期内要执行的操作的结果与来自指令解码逻辑的控制信号相反的操作算术逻辑单元（ALU）的方法，该指令解码逻辑指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。

公开(公告)号：US20080162618A1

公开(公告)日：2008-07-03

申请号：US12047525

申请日：2008-03-13

申请人： FADI Y. BUSABA ,  Lawrence Joseph Powell ,  Martin Stanley Schmookler ,  Michael Thomas Vaden ,  David Allan Webber

发明人： FADI Y. BUSABA ,  Lawrence Joseph Powell ,  Martin Stanley Schmookler ,  Michael Thomas Vaden ,  David Allan Webber

IPC分类号： G06F11/20

CPC分类号： G06F11/2226

摘要： A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

摘要翻译： 公开了一种发现电路故障的方法。 该方法包括通过在操作数上执行所选功能来产生所选功能的第一结果，其中所选功能采用掩码。 一旦执行了该功能，就产生一个掩模的防范，并计算出锑的模数。 计算所选函数的第一结果的模函数以获得第三结果。 然后计算操作数的模以获得第四结果，然后对第二结果和第三结果执行第二函数以获得第五结果。 响应于将第五结果与第四结果进行比较，传播信号以指示电路中的故障。