公开(公告)号：US20110019368A1

公开(公告)日：2011-01-27

申请号：US12507591

申请日：2009-07-22

申请人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

发明人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

IPC分类号： H05K1/18 ,  C23F1/00

CPC分类号： H01L25/0655 ,  H01L23/147 ,  H01L23/60 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/157 ,  Y02T10/82 ,  H01L2924/00

摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

摘要翻译： 一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片 硅载体衬底和设置在硅载体衬底上的时钟芯片。

公开(公告)号：US20130024400A1

公开(公告)日：2013-01-24

申请号：US13184832

申请日：2011-07-18

申请人： Casimer M. DeCusatis ,  George A. Katopis ,  Roger S. Krabbenhoft ,  Todd A. Nelson ,  Sreekanth Ramakrishnan ,  Anuradha Rao ,  Joseph H. Torella

发明人： Casimer M. DeCusatis ,  George A. Katopis ,  Roger S. Krabbenhoft ,  Todd A. Nelson ,  Sreekanth Ramakrishnan ,  Anuradha Rao ,  Joseph H. Torella

IPC分类号： G06Q10/00

CPC分类号： G06F17/5068

摘要： A total cost estimate is calculated based on a set of printed circuit board (PCB) design parameters. The set of PCB design parameters are received, and PCB attributes are extracted from them. Based on the PCB attributes the PCB is classified and a cost equation is calculated. The cost equation is calculated based on a regression analysis of one or more of the PCB attributes. Once the cost equation is calculated, the total cost is computed based on the cost equation.

摘要翻译： 基于一组印刷电路板（PCB）设计参数计算总成本估算。 接收一组PCB设计参数，并从中提取PCB属性。 根据PCB属性对PCB进行分类，并计算成本方程。 成本方程是根据一个或多个PCB属性的回归分析计算的。 一旦计算了成本方程，总成本就是根据成本方程计算的。

公开(公告)号：US20120301977A1

公开(公告)日：2012-11-29

申请号：US13569872

申请日：2012-08-08

申请人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

发明人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

IPC分类号： H01L21/66 ,  G06F17/50

CPC分类号： H01L25/0655 ,  H01L23/147 ,  H01L23/60 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/00

摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

摘要翻译： 一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片 硅载体衬底和设置在硅载体衬底上的时钟芯片。

公开(公告)号：US08227264B2

公开(公告)日：2012-07-24

申请号：US13071894

申请日：2011-03-25

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L21/30

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US07936060B2

公开(公告)日：2011-05-03

申请号：US12431827

申请日：2009-04-29

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L23/52

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US20100277197A1

公开(公告)日：2010-11-04

申请号：US12432082

申请日：2009-04-29

申请人： Alina Deutsch ,  George A. Katopis ,  Gerard V. Kopcsay ,  Roger S. Krabbenhoft ,  Christopher W. Surovic

发明人： Alina Deutsch ,  George A. Katopis ,  Gerard V. Kopcsay ,  Roger S. Krabbenhoft ,  Christopher W. Surovic

IPC分类号： G01R31/02

CPC分类号： G01R31/2818 ,  G01R31/2822

摘要： A system and method for performing a test for characterizing high frequency operation of PCB boards. More particularly, a system and methodology is provided to implement a time-domain short pulse propagation (SPP) technique on the production line, on large, multi-layer, product-level PCB boards, for large volume testing, by people who are not familiar with advanced, delicate, measurement techniques, who need robust test facilities, and cannot afford the time or expense of other lab-type approaches.

摘要翻译： 一种执行PCB板高频运行特性测试的系统和方法。 更具体地，提供了一种系统和方法，用于在生产线上，在大型，多层，产品级PCB板上实施时域短脉冲传播（SPP）技术，用于大容量测试，由不是 熟悉先进，精细，测量技术，需要强大的测试设施，无法承担其他实验室方法的时间或费用。

公开(公告)号：US20110171756A1

公开(公告)日：2011-07-14

申请号：US13071894

申请日：2011-03-25

申请人： Paul S. ANDRY ,  Stephen L. BUCHWALTER ,  George A. KATOPIS ,  John U. KNICKERBOCKER ,  Stelios G. TSAPEPAS ,  Bucknell C. WEBB

发明人： Paul S. ANDRY ,  Stephen L. BUCHWALTER ,  George A. KATOPIS ,  John U. KNICKERBOCKER ,  Stelios G. TSAPEPAS ,  Bucknell C. WEBB

IPC分类号： H01L21/30 ,  H01L21/50

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US5970052A

公开(公告)日：1999-10-19

申请号：US933574

申请日：1997-09-19

申请人： Tin-Chee Lo ,  George A. Katopis ,  Timothy Gerard McNamara ,  David Allan Webber ,  Joseph L. Braun ,  Paul R. Turgeon

发明人： Tin-Chee Lo ,  George A. Katopis ,  Timothy Gerard McNamara ,  David Allan Webber ,  Joseph L. Braun ,  Paul R. Turgeon

IPC分类号： G01R31/3173 ,  G06F11/267

CPC分类号： G06F11/221 ,  G01R31/3173

摘要： A method for dynamic bandwidth testing of a link between two computer subsystems useful for determining the amount of data which can be buffered in a transmission line by delay, in which at each end of the line circuit modules are provided to couple the subsystem by a bi-directional multi-bit (BiDi) link, and providing within each said circuit module a built-in circuit and logic for dynamic transmission characterization and test of a said BiDi link between computer subsystems using built-in characterization logic macros, and during a test mode, switching said said built-in circuit and logic to test mode and using the test mode to characterize the link performance, and after the completion of characterization, the switching built-in characterization logic macros back to a normal system mode after programmatically setting timing parameters for the BiDi link to ensure safe operation of data transfer before the BiDi link is switched to system mode.

摘要翻译： 一种用于在两个计算机子系统之间的链路的动态带宽测试的方法，其用于确定可以通过延迟在传输线路中缓冲的数据量，其中在线路电路模块的每一端被提供以通过bi耦合子系统 并且在每个所述电路模块内提供内置电路和逻辑，用于使用内置的表征逻辑宏以及在测试期间对计算机子系统之间的所述BiDi链路进行动态传输表征和测试 模式，将所述内置电路和逻辑切换到测试模式并使用测试模式来表征链路性能，并且在表征完成之后，通过编程设置定时将交换内置表征逻辑宏恢复到正常的系统模式 BiDi链路的参数，以确保在BiDi链路切换到系统模式之前数据传输的安全运行。

公开(公告)号：US5477460A

公开(公告)日：1995-12-19

申请号：US360519

申请日：1994-12-21

申请人： Charles K. Vakirtzis ,  George A. Katopis ,  Gerald W. Mahoney ,  Craig R. Selinger ,  Bradley D. McCredie ,  Wiren D. Becker

发明人： Charles K. Vakirtzis ,  George A. Katopis ,  Gerald W. Mahoney ,  Craig R. Selinger ,  Bradley D. McCredie ,  Wiren D. Becker

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Switching characteristics of system components are represented and summed so that their effects on the overall system can be observed during the design process. Full simultaneous switching analysis is provided at the earliest levels of design containing minimal level of design data by a method of computing net based simultaneous switching noise levels which supports packages ranging from the smallest chip level to the largest board level. The simultaneous switching activity is computed based on interaction between each driver and each other driver between each component and each other component, with consideration to the spatial inter-relationship net, within a higher level component, to determine each component's drivers effect on itself as well as the coupling effect between drivers on different components. The analysis involves computing simultaneous switching noise by associating a characteristic triangle with each driver application configuration. The characteristic triangle. The height of the triangle, as well as the pitch of the sides of the triangle will be determined by the characteristics of the net. In the early stages of design, a default characteristic triangle is defined for each technology type. A general triangle is also defined for cases where early analysis needs to be performed prior to choosing a technology.

摘要翻译： 系统组件的开关特性被表示和相加，以便在设计过程中可以观察到它们对整个系统的影响。 通过计算基于网络的同步开关噪声电平的方法，提供了最初设计的包含最小级别的设计数据的全面同步开关分析，该方法支持从最小芯片级到最大板级的封装。 基于每个组件和每个其他组件之间的每个驱动程序和每个其他驱动程序之间的相互作用计算同时切换活动，考虑到较高级组件内的空间相互关系网，以确定每个组件的驱动程序对其本身的影响 作为不同组件上的驱动程序之间的耦合效应。 分析涉及通过将特征三角形与每个驱动程序应用程序配置相关联来计算同时切换噪声。 特征三角形。 三角形的高度以及三角形边的间距将由网络的特性决定。 在设计的早期阶段，为每种技术类型定义默认特征三角形。 对于在选择技术之前需要进行早期分析的情况，也定义了一般三角形。

公开(公告)号：US4398106A

公开(公告)日：1983-08-09

申请号：US218150

申请日：1980-12-19

申请人： Evan E. Davidson ,  George A. Katopis ,  Barry J. Rubin

发明人： Evan E. Davidson ,  George A. Katopis ,  Barry J. Rubin

IPC分类号： H03K19/0175 ,  G05F1/46 ,  H01L27/00 ,  H01L27/01 ,  H04B15/00 ,  H04L25/08 ,  H03H11/46 ,  H03H5/12

CPC分类号： G05F1/467

摘要： A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. An impedance path is defined between each of the chips and the power supply to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.

摘要翻译： 一种用于在多芯片模块半导体结构中减少自感应开关噪声的钳位电路。 模块部分互连芯片，芯片分别具有电源和电源引线。 在每个芯片和电源之间限定阻抗路径，以限定用于通过模块顶部切换噪声的电流路径。 对于低于芯片电源电压的预定上限的电压，限定高阻抗路径，并且在钳位电路中限定出叠加在芯片电源电压上的噪声的电压范围的低阻抗路径。