公开(公告)号：US20140125883A1

公开(公告)日：2014-05-08

申请号：US14072811

申请日：2013-11-06

Applicant: Ting-Yu Chang ,  Kuo-Chang Su

Inventor： Ting-Yu Chang ,  Kuo-Chang Su

IPC: G06F1/16

CPC classification number: G06F1/1692 ,  G06F3/044

Abstract: A touch panel, including a substrate, first electrodes, second electrodes, first connecting lines, first pads, second connecting lines, and second pads, is provided. The first electrodes are arranged in an array to define a plurality of columns each parallel to a first direction and a plurality of rows each parallel to a second direction intersecting the first direction. Each of the second electrodes is extended in the first direction. The second electrodes are sequentially arranged in the second direction so that one column of the first electrodes is disposed between two adjacent second electrodes. The first connecting lines connect the first electrodes in the same row into a series connected to one first pad. The second electrodes are connected to the second pads through the second connecting lines. The first electrodes, the second electrodes, the first connecting lines, and the second connecting lines do not intersect one another.

Abstract translation: 提供了包括基板，第一电极，第二电极，第一连接线，第一焊盘，第二连接线和第二焊盘的触摸面板。 第一电极被排列成阵列以限定平行于第一方向的多个列，以及平行于与第一方向相交的第二方向的多个行。 每个第二电极在第一方向上延伸。 第二电极依次布置在第二方向上，使得一列第一电极设置在两个相邻的第二电极之间。 第一连接线将同一行中的第一电极连接到连接到一个第一焊盘的串联中。 第二电极通过第二连接线连接到第二焊盘。 第一电极，第二电极，第一连接线和第二连接线彼此不相交。

公开(公告)号：US09323295B2

公开(公告)日：2016-04-26

申请号：US14072811

申请日：2013-11-06

Applicant: Ting-Yu Chang ,  Kuo-Chang Su

Inventor： Ting-Yu Chang ,  Kuo-Chang Su

IPC: G06F3/045 ,  G06F1/16 ,  G06F3/044

CPC classification number: G06F1/1692 ,  G06F3/044

Abstract: A touch panel, including a substrate, first electrodes, second electrodes, first connecting lines, first pads, second connecting lines, and second pads, is provided. The first electrodes are arranged in an array to define a plurality of columns each parallel to a first direction and a plurality of rows each parallel to a second direction intersecting the first direction. Each of the second electrodes is extended in the first direction. The second electrodes are sequentially arranged in the second direction so that one column of the first electrodes is disposed between two adjacent second electrodes. The first connecting lines connect the first electrodes in the same row into a series connected to one first pad. The second electrodes are connected to the second pads through the second connecting lines. The first electrodes, the second electrodes, the first connecting lines, and the second connecting lines do not intersect one another.

Abstract translation: 提供了包括基板，第一电极，第二电极，第一连接线，第一焊盘，第二连接线和第二焊盘的触摸面板。 第一电极被排列成阵列以限定平行于第一方向的多个列，以及平行于与第一方向相交的第二方向的多个行。 每个第二电极在第一方向上延伸。 第二电极依次布置在第二方向上，使得一列第一电极设置在两个相邻的第二电极之间。 第一连接线将同一行中的第一电极连接到连接到一个第一焊盘的串联中。 第二电极通过第二连接线连接到第二焊盘。 第一电极，第二电极，第一连接线和第二连接线彼此不相交。

公开(公告)号：US08970467B2

公开(公告)日：2015-03-03

申请号：US12727287

申请日：2010-03-19

Applicant: Chien-Ting Chan ,  Wen-Chun Wang ,  Hsi-Rong Han ,  Kuo-Chang Su

Inventor： Chien-Ting Chan ,  Wen-Chun Wang ,  Hsi-Rong Han ,  Kuo-Chang Su

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286

Abstract: A shift register including a plurality of multi-stage shift register circuits is provided. The mth stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mth period, is defined on the node. The shift register unit is controlled by an (m−1)th stage output signal provided by an (m−1)th stage shift register circuit and a clock signal for providing the enabled mth stage output signal in the mth period, and controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing a disenabled mth stage output signal in the (m+1)th period. The control circuit, controlled by the clock signal, provides and outputs an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal, wherein m is a natural number greater than 1.

Abstract translation: 提供了包括多个多级移位寄存器电路的移位寄存器。 第m级移位寄存器电路包括一个节点，一个移位寄存器单元和一个控制电路。 节点上定义了第m个周期启用的第一个控制信号。 移位寄存器单元由第（m-1）级移位寄存器电路提供的第（m-1）级输出信号和用于在第m个周期中提供使能的第m级输出信号的时钟信号控制，并由 由第（m + 1）级移位寄存器电路提供的第（m + 1）级第二控制信号，用于在第（m + 1）个周期中提供不能使用的第m级输出信号。 由时钟信号控制的控制电路根据第m级第一控制信号向第（m-1）级移位寄存器电路提供第m级第二控制信号，其中m是大于1的自然数。

公开(公告)号：US20140152915A1

公开(公告)日：2014-06-05

申请号：US14093032

申请日：2013-11-28

Applicant: Chia-Ching Lu ,  Kuo-Chang Su ,  Chen-Hao Su ,  Cheng-Yen Yeh ,  Yu-Ting Chen

Inventor： Chia-Ching Lu ,  Kuo-Chang Su ,  Chen-Hao Su ,  Cheng-Yen Yeh ,  Yu-Ting Chen

IPC: G06F1/16

CPC classification number: G06F1/1643 ,  G06F3/044

Abstract: A touch panel includes a substrate, a plurality of first and second conductive series, and a plurality of first and second auxiliary electrodes. The first and the second conductive series are disposed alternately on the substrate and located on a light-transmission area of the substrate. A portion of each of the first and second conductive series extends to a peripheral area of the substrate. The first and the second auxiliary electrodes are disposed on the peripheral area. The first auxiliary electrodes connect to the portion of the first conductive series extending to the peripheral area and generate capacitive sensing with the portion of the second conductive series located on the peripheral area. The second auxiliary electrodes connect to the portion of the second conductive series extending to the peripheral area and generate capacitive sensing with the portion of the first conductive series located on the peripheral area.

Abstract translation: 触摸面板包括基板，多个第一和第二导电系列以及多个第一和第二辅助电极。 第一和第二导电系列交替地设置在基板上并且位于基板的光透射区域上。 第一和第二导电系列中的每一个的一部分延伸到衬底的周边区域。 第一辅助电极和第二辅助电极设置在周边区域上。 第一辅助电极连接到延伸到周边区域的第一导电串联的部分，并且产生电容感测，其中第二导电系列的部分位于周边区域上。 第二辅助电极连接到延伸到周边区域的第二导电串联的部分，并且产生电容感测，第一导电系列的位于周边区域的部分。

公开(公告)号：US08456454B2

公开(公告)日：2013-06-04

申请号：US12488946

申请日：2009-06-22

Applicant: Yung-Chih Chen ,  Chun-Hsin Liu ,  Tsung-Ting Tsai ,  Kuo-Chang Su

Inventor： Yung-Chih Chen ,  Chun-Hsin Liu ,  Tsung-Ting Tsai ,  Kuo-Chang Su

IPC: G06F3/038 ,  G09G5/00 ,  G02F1/1333

CPC classification number: G09G3/3677 ,  G09G2300/0426 ,  G09G2330/08 ,  G09G2330/12

Abstract: A display panel is disclosed, which includes a substrate, a shift register array, plural scan lines, a compensating circuit, a first repair line, and a second repair line. The shift register array having plural shift registers is disposed on a non-display area of the substrate. The scan lines connect to the shift registers respectively to drive plural display units. The first repair line and the second repair line are connected to the compensating circuit and bridged over two ends of each scan line in the non-display area, respectively.

Abstract translation: 公开了一种显示面板，其包括基板，移位寄存器阵列，多条扫描线，补偿电路，第一修复线和第二修复线。 具有多个移位寄存器的移位寄存器阵列设置在基板的非显示区域上。 扫描线分别连接到移位寄存器以驱动多个显示单元。 第一修理线和第二修复线分别连接到补偿电路并桥接在非显示区域中的每条扫描线的两端。

公开(公告)号：US08410485B2

公开(公告)日：2013-04-02

申请号：US13080664

申请日：2011-04-06

Applicant: Chin-Chang Liu ,  Chien-Ting Chan ,  Kuo-Chang Su

Inventor： Chin-Chang Liu ,  Chien-Ting Chan ,  Kuo-Chang Su

IPC: H01L29/04

CPC classification number: G02F1/1368 ,  H01L27/12 ,  H01L27/124

Abstract: A pixel structure including a scan line, a data line intersecting the scan line, a first gate, a second gate, a third gate, a semiconductor layer, a source, a first drain, a second drain, a first pixel electrode, and a second pixel electrode is provided. The dataline and the scan line are interlaced disposed. The semiconductor layer is disposed on the scan line to define the first gate and the second gate. The source is directly connected to the data line and located between the first gate and the second gate. The first gate is located between the first drain and the source. The second gate is located between the second drain and the source. The third gate is electrically connected to the scan line. The first pixel electrode and the second pixel electrode are respectively electrically connected to the first drain and the second drain.

Abstract translation: 包括扫描线，与扫描线相交的数据线的像素结构，第一栅极，第二栅极，第三栅极，半导体层，源极，第一漏极，第二漏极，第一像素电极和 提供第二像素电极。 数据线和扫描线交错布置。 半导体层设置在扫描线上以限定第一栅极和第二栅极。 源极直接连接到数据线并且位于第一栅极和第二栅极之间。 第一个栅极位于第一个漏极和源极之间。 第二个栅极位于第二个漏极和源极之间。 第三栅极电连接到扫描线。 第一像素电极和第二像素电极分别电连接到第一漏极和第二漏极。

公开(公告)号：US08396183B2

公开(公告)日：2013-03-12

申请号：US13049863

申请日：2011-03-16

Applicant: Yu-Chung Yang ,  Yung-Chih Chen ,  Kuo-Hua Hsu ,  Kuo-Chang Su

Inventor： Yu-Chung Yang ,  Yung-Chih Chen ,  Kuo-Hua Hsu ,  Kuo-Chang Su

IPC: G11C19/00

CPC classification number: G09G3/20 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit, a pull-up unit, a pull-down unit, a control unit and an auxiliary pull-down unit. The input unit is put in use for outputting a driving control voltage according to at least one first input signal. The pull-up unit pulls up a corresponding gate signal according to the driving control voltage and a system clock. The pull-down unit pulls down the corresponding gate signal to a first power voltage according to a control signal. The control unit is utilized for generating the control signal according to the corresponding gate signal. The auxiliary pull-down unit pulls down the driving control voltage to a second power voltage according to a second input signal.

Abstract translation: 移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。 每个移位寄存器级包括输入单元，上拉单元，下拉单元，控制单元和辅助下拉单元。 输入单元被用于根据至少一个第一输入信号输出驱动控制电压。 上拉单元根据驱动控制电压和系统时钟提取相应的门信号。 下拉单元根据控制信号将相应的门信号拉低至第一电源电压。 控制单元用于根据相应的门信号产生控制信号。 辅助下拉单元根据第二输入信号将驱动控制电压下拉到第二电源电压。

公开(公告)号：US08175215B2

公开(公告)日：2012-05-08

申请号：US12572247

申请日：2009-10-01

Applicant: Chun-Hsin Liu ,  Tsung-ting Tsai ,  Kuo-Chang Su ,  Yung-Chih Chen

Inventor： Chun-Hsin Liu ,  Tsung-ting Tsai ,  Kuo-Chang Su ,  Yung-Chih Chen

IPC: G11C19/00

CPC classification number: G11C19/28

Abstract: A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.

Abstract translation: 移位寄存器包括多个级联连接级。 每一级响应于时钟信号和第一控制信号产生输出信号。 每个级包括上拉模块，上拉驱动模块，第一下拉模块，第二下拉模块和第三下拉模块。 上拉模块用于根据时钟信号提供输出信号。 上拉驱动模块响应于第一控制信号而导通上拉模块。 第一下拉模块响应于第二控制信号将第一节点上的电压电平调整到第一电源电压。 第二下拉模块响应于第二控制信号将输出端上的电压电平调整到第二电源电压。 第三下拉模块响应于第三控制信号将第二节点上的电压电平调整到第三电源电压。

公开(公告)号：US08027426B1

公开(公告)日：2011-09-27

申请号：US12837244

申请日：2010-07-15

Applicant: Yu-Chung Yang ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Chun-Hsin Liu

Inventor： Yu-Chung Yang ,  Kuo-Chang Su ,  Yung-Chih Chen ,  Chun-Hsin Liu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G2310/0286 ,  G11C19/184

Abstract: An exemplary shift register includes a plurality of transistors. The transistors are subjected to the control of a start pulse signal, a first clock signal and a second clock signal to generate a gate driving signal. The first clock signal and the second clock signal are phase-inverted with respect to each other. A logic low level of the first clock signal and another logic low level of the second clock signal are different from each other. Moreover, the transistors are negative threshold voltage transistors. A potential at the gate of the each of the transistors is lower than another potential at the source/drain of the transistor at the situation of the transistor being switched-off state.

Abstract translation: 示例性移位寄存器包括多个晶体管。 对晶体管进行起始脉冲信号，第一时钟信号和第二时钟信号的控制，以产生栅极驱动信号。 第一时钟信号和第二时钟信号相对于彼此相位反相。 第一时钟信号的逻辑低电平和第二时钟信号的另一个逻辑低电平彼此不同。 而且，晶体管是负阈值电压晶体管。 在晶体管处于截止状态的情况下，每个晶体管的栅极处的电位低于晶体管的源极/漏极处的另一个电位。

公开(公告)号：US20110002437A1

公开(公告)日：2011-01-06

申请号：US12607156

申请日：2009-10-28

Applicant: Kuo-Chang Su ,  Tsung-Ting Tsai ,  Yung-Chih Chen ,  Chun-Hsin Liu

Inventor： Kuo-Chang Su ,  Tsung-Ting Tsai ,  Yung-Chih Chen ,  Chun-Hsin Liu

IPC: G11C19/00

CPC classification number: G11C19/28

Abstract: A shift register is provided and includes a first shift registering unit and a second shift registering unit. The first shift registering unit generates a first trigger signal at a first output terminal and includes a first pull-down circuit. The second shift registering unit receives the first trigger signal and generates a second trigger signal at a second output terminal. The first trigger signal and the second trigger signal are sequentially asserted. The second shift registering unit includes a second pull-down circuit. The first pull-down circuit and the second pull-down circuit perform pull-down operations at different times. When the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal.

Abstract translation: 提供一个移位寄存器，包括一个第一移位寄存单元和一个第二移位寄存单元。 第一移位寄存单元在第一输出端产生第一触发信号，并包括第一下拉电路。 第二移位寄存单元接收第一触发信号并在第二输出端产生第二触发信号。 第一触发信号和第二触发信号被依次断言。 第二移位登记单元包括第二下拉电路。 第一下拉电路和第二下拉电路在不同时间执行下拉操作。 当第一下拉电路不执行下拉操作时，第二下拉电路对第一输出端子执行下拉操作。