公开(公告)号：US20120005516A1

公开(公告)日：2012-01-05

申请号：US13170466

申请日：2011-06-28

申请人： Tobias BERGMANN ,  Ralf LUDEWIG ,  Tobias WEBEL ,  Ulrich WEISS

发明人： Tobias BERGMANN ,  Ralf LUDEWIG ,  Tobias WEBEL ,  Ulrich WEISS

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  G06F1/3237 ,  Y02D10/128

摘要： A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

摘要翻译： 提供一种计算机系统，其包括多个节点，其包括不同类型的芯片。 在每个节点中，一个芯片被配置为主芯片，其通过两个或更多个多点网络（例如，checkstop，clockrun）连接到一个或多个从芯片。 主芯片和从芯片连接到参考时钟，事件触发信息通过多点网络（checkstop，clockrun）发送到从芯片。 事件触发命令由主芯片在接收到请求时提交，内部偏移计数器用于在命令传播到芯片上的单元时调整接收周期和周期。 在运行中，偏移计数器由参考时钟同步。