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    Synchronous clock stop in a multi nodal computer system
    3.
    发明授权
    Synchronous clock stop in a multi nodal computer system 有权
    多节点计算机系统中的同步时钟停止

    公开(公告)号：US08868960B2

    公开(公告)日：2014-10-21

    申请号：US13170466

    申请日：2011-06-28

    申请人： Tobias Bergmann ,  Ralf Ludewig ,  Tobias Webel ,  Ulrich Weiss

    发明人： Tobias Bergmann ,  Ralf Ludewig ,  Tobias Webel ,  Ulrich Weiss

    IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F15/16 ,  G06F1/32

    CPC分类号： G06F1/12 ,  G06F1/3237 ,  Y02D10/128

    摘要： A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

    摘要翻译： 提供一种计算机系统，其包括多个节点，其包括不同类型的芯片。 在每个节点中，一个芯片被配置为主芯片，其通过两个或更多个多点网络（例如，checkstop，clockrun）连接到一个或多个从芯片。 主芯片和从芯片连接到参考时钟，事件触发信息通过多点网络（checkstop，clockrun）发送到从芯片。 事件触发命令由主芯片在接收到请求时提交，内部偏移计数器用于在命令传播到芯片上的单元时调整接收周期和周期。 在运行中，偏移计数器由参考时钟同步。

    CLOCK SIGNALS IN DIGITAL SYSTEMS
    4.
    发明申请
    CLOCK SIGNALS IN DIGITAL SYSTEMS 有权
    数字系统中的时钟信号

    公开(公告)号：US20090217000A1

    公开(公告)日：2009-08-27

    申请号：US12236551

    申请日：2008-09-24

    申请人： Jeffrey A. Magee ,  Timothy Gerard McNamara ,  Walter Niklaus ,  Scott Barnett Swaney ,  Tobias Webel

    发明人： Jeffrey A. Magee ,  Timothy Gerard McNamara ,  Walter Niklaus ,  Scott Barnett Swaney ,  Tobias Webel

    IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F15/76 ,  G06F9/02

    CPC分类号： G06F9/3869 ,  G01R31/318533 ,  G01R31/318558

    摘要： A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

    摘要翻译： 数字系统及其操作方法。 该系统包括包括第一弹性接口域的处理器芯片，其中第一弹性接口域包括第一处理器X逻辑和第一处理器Y逻辑，其中第一处理器X和Y逻辑分别包括第一X和Y锁存器; 以及电耦合到所述处理器芯片的第一ASIC芯片，其中所述第一处理器X和Y逻辑被配置为同时处于功能模式，其中所述第一处理器X逻辑被配置为从所述功能模式切换到扫描模式，而 第一处理器Y逻辑保持在功能模式中，并且其中响应于第一处理器Y逻辑处于功能模式，第一处理器Y逻辑被配置为产生到第一ASIC芯片的第一参考ASIC时钟信号。

    Fault Tolerant Time Synchronization Mechanism in a Scaleable Multi-Processor Computer
    6.
    发明申请
    Fault Tolerant Time Synchronization Mechanism in a Scaleable Multi-Processor Computer 失效
    可扩展多处理器计算机中的容错时间同步机制

    公开(公告)号：US20080244300A1

    公开(公告)日：2008-10-02

    申请号：US12140028

    申请日：2008-06-16

    申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

    发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

    IPC分类号： G06F1/12

    CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

    摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

    摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

    Accounting for Microprocessor Resource Consumption
    7.
    发明申请
    Accounting for Microprocessor Resource Consumption 失效
    计算微处理器资源消耗

    公开(公告)号：US20080209245A1

    公开(公告)日：2008-08-28

    申请号：US12029636

    申请日：2008-02-12

    申请人： Daniel Becker ,  Rafael Keggenhoff ,  Thuyen Le ,  Tobias Webel ,  Matthias Woehrle

    发明人： Daniel Becker ,  Rafael Keggenhoff ,  Thuyen Le ,  Tobias Webel ,  Matthias Woehrle

    IPC分类号： G06F1/06 ,  G06F1/32

    CPC分类号： G06F11/3058 ,  G06F11/3024 ,  G06F11/3419 ,  G06F11/348

    摘要： Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

    摘要翻译： 用于会计微处理器资源消耗的技术。 本发明提供了一种能够及时确定当前微处理器时钟频率的自动方法。 由微处理器的定时器设备提供的信息通过以恒定的间隔对该信息进行采样来重用。 微处理器时钟频率的这种直接推导是一种也考虑到二次效应的实时方法。 这种二次效应的示例包括由于制造变化导致的芯片之间的时钟频率变化，由于热损耗导致的任何劣化或其他有害影响以及任何电压变化。 在本发明的优选实施例中，实时微处理器时钟频率确定被实现为微处理器本身的一部分。 为了控制微处理器的时钟频率确定功能，不需要附加的服务处理器或其他外部硬件设备。

    Redundant oscillator distribution in a multi-processor server system
    8.
    发明授权
    Redundant oscillator distribution in a multi-processor server system 失效
    多处理器服务器系统中的冗余振荡器分布

    公开(公告)号：US07308592B2

    公开(公告)日：2007-12-11

    申请号：US11056009

    申请日：2005-02-11

    申请人： Dietmar Schmunkamp ,  Andreas Wagner ,  Tobias Webel ,  Ulrich Weiss

    发明人： Dietmar Schmunkamp ,  Andreas Wagner ,  Tobias Webel ,  Ulrich Weiss

    IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00

    CPC分类号： G06F11/1604 ,  G06F11/20

    摘要： The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.

    摘要翻译： 本发明涉及计算机系统中的系统时钟。 特别地，它涉及具有增强的性能和可靠性程度的高端多处理器，多节点服务器计算机系统中的系统时钟以及用于在第一和第二时钟信号之间动态切换的方法，如果第一应用 失败。 提供了更多的冗余，即使是动态时钟切换电路（DCSC）（14）和布线（17），也可以是多个PLL-（12）空闲时钟芯片（22）。 而不是只有一个DCSC（14）和一个单个布线（17），它们中的两个（14 - 0，14 - 1，17 - 0，17 - 1）与每个时钟芯片上存在的另一个特定逻辑 22），其组合产生两个同步，微调的最小移位时钟信号，并总是选择第一个来获得控制时钟分配布线输出的FlipFlop。

    Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes
    9.
    发明授权
    Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes 有权
    在处理器接口中为耦合ASIC芯片生成时钟信号，X和Y逻辑可在功能和扫描模式下运行

    公开(公告)号：US08090929B2

    公开(公告)日：2012-01-03

    申请号：US12236551

    申请日：2008-09-24

    申请人： Jeffrey A. Magee ,  Timothy Gerard McNamara ,  Walter Niklaus ,  Scott Barnett Swaney ,  Tobias Webel

    发明人： Jeffrey A. Magee ,  Timothy Gerard McNamara ,  Walter Niklaus ,  Scott Barnett Swaney ,  Tobias Webel

    IPC分类号： G06F1/04

    CPC分类号： G06F9/3869 ,  G01R31/318533 ,  G01R31/318558

    摘要： A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

    摘要翻译： 数字系统及其操作方法。 该系统包括包括第一弹性接口域的处理器芯片，其中第一弹性接口域包括第一处理器X逻辑和第一处理器Y逻辑，其中第一处理器X和Y逻辑分别包括第一X和Y锁存器; 以及电耦合到所述处理器芯片的第一ASIC芯片，其中所述第一处理器X和Y逻辑被配置为同时处于功能模式，其中所述第一处理器X逻辑被配置为从所述功能模式切换到扫描模式，而 第一处理器Y逻辑保持在功能模式中，并且其中响应于第一处理器Y逻辑处于功能模式，第一处理器Y逻辑被配置为产生到第一ASIC芯片的第一参考ASIC时钟信号。

    Method and apparatus for automatic scan completion in the event of a system checkstop
    10.
    发明授权
    Method and apparatus for automatic scan completion in the event of a system checkstop 失效
    在系统检查停止的情况下自动扫描完成的方法和装置

    公开(公告)号：US07966536B2

    公开(公告)日：2011-06-21

    申请号：US12101208

    申请日：2008-04-11

    申请人： Ralf Ludewig ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Tobias Webel

    发明人： Ralf Ludewig ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Tobias Webel

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G06F11/0784 ,  G06F11/0706 ,  G06F11/0778 ,  G06F11/2236

    摘要： A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.

    摘要翻译： 在处理器中系统检查停止时自动扫描完成的方法。 处理器包括：处理器寄存器; 连接在处理器寄存器和检查站扫描控制器之间的millicode接口; 连接在止回扫描控制器和检查停止扫描引擎之间的止回逻辑电路; 以及连接到检查停止扫描引擎的扫描链引擎和扫描链。 该方法包括（a）在发生从处理器寄存器串行读取数据的检查站并将数据串行写入扫描链寄存器的锁存器时; 和（b）在（a）期间发生系统检查停止时，停止在系统检查停止期间发送的读取和写入数据，并且在发生系统检查停止时存储数据的扫描链的锁存器中移动数据，以锁定数据将在哪里 如果没有发生系统检查停止，则已存储。