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    ABIST-assisted detection of scan chain defects
    1.
    发明申请
    ABIST-assisted detection of scan chain defects 有权
    ABIST辅助检测扫描链缺陷

    公开(公告)号：US20050138514A1

    公开(公告)日：2005-06-23

    申请号：US10728348

    申请日：2003-12-04

    申请人： Todd Burdine ,  Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Steven Michnowski ,  James Webb

    发明人： Todd Burdine ,  Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Steven Michnowski ,  James Webb

    IPC分类号： G01R31/3185 ,  G11B5/00 ,  G01R31/28 ,  G06K5/04 ,  G11B20/20

    CPC分类号： G01R31/318569

    摘要： An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.

    摘要翻译： 一种装置，程序产品和方法利用在集成电路装置上提供的ABIST电路来帮助识别和定位也在集成电路装置上提供的扫描链中的缺陷。 特别地，可以通过将多个图案组应用于耦合到ABIST电路的扫描链来检测扫描链中的缺陷，从而将由多个图案组应用的结果生成的数据收集到扫描链中 并且使用所收集的扫描数据来识别扫描链中的有缺陷的锁存器。

    Method and system for determining repeatable yield detractors of integrated circuits
    3.
    发明授权
    Method and system for determining repeatable yield detractors of integrated circuits 失效
    用于确定集成电路的可重复产量剔除器的方法和系统

    公开(公告)号：US06751765B1

    公开(公告)日：2004-06-15

    申请号：US09722880

    申请日：2000-11-27

    申请人： Richard F. Rizzolo ,  Rocco E. DeStefano ,  Joseph E. Eckelman ,  Thomas G. Foote ,  Steven Michnowski ,  Franco Motika ,  Phillip J. Nigh ,  Bryan J. Robbins

    发明人： Richard F. Rizzolo ,  Rocco E. DeStefano ,  Joseph E. Eckelman ,  Thomas G. Foote ,  Steven Michnowski ,  Franco Motika ,  Phillip J. Nigh ,  Bryan J. Robbins

    IPC分类号： G01R3128

    CPC分类号： G01R31/3185

    摘要： An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.

    摘要翻译： 本发明的示例性实施例是用于LBIST测试集成电路的方法。 该方法包括生成多个多位测试模式，并且通过多个测试模式分区对多位测试模式进行分组，所述多个测试模式分区包括具有第一数量位的第一测试模式分区和具有第二数量位的第二测试模式分区 大于第一个数字。 将第一测试模式分区应用于集成电路以生成与第一参考签名进行比较以检测故障的第一签名。 将第二测试模式分区应用于集成电路以产生与第二参考签名进行比较的第二签名，以检测集成电路中的故障。