公开(公告)号：US06442514B1

公开(公告)日：2002-08-27

申请号：US09205328

申请日：1998-12-04

申请人： Tony Viet Nam Le

发明人： Tony Viet Nam Le

IPC分类号： G06F944

CPC分类号： G06F11/261 ,  G06F17/5022

摘要： A method and system for simulation of a communications bus. A simulation arrangement is configured with a behavioral agent and an application agent coupled to the bus. Bus commands are selectively loaded in the behavioral and application agent in accordance with a desired simulation sequence. The behavioral agent is configurable with phase behavior instructions that specify assertion and deassertion times for selected signals by the behavioral agent. Compliant and non-compliant bus behavior can be simulated with the phase behavior instructions.

摘要翻译： 一种用于模拟通信总线的方法和系统。 模拟布置被配置有与总线耦合的行为代理和应用代理。 总线命令根据期望的模拟序列选择性地加载到行为和应用代理中。 行为代理可配置相位行为指令，其指定行为代理对所选信号的断言和解除停机时间。 可以使用相位行为指令来模拟符合标准和不符合标准的总线行为。

公开(公告)号：US06434517B1

公开(公告)日：2002-08-13

申请号：US09205829

申请日：1998-12-04

申请人： Tony Viet Nam Le

发明人： Tony Viet Nam Le

IPC分类号： G06F9455

CPC分类号： G06F11/261 ,  G06F17/5022

摘要： A method and system for demonstrating simulation of a communications bus. In various embodiments, methods and systems are described which support recording a simulation of a system having a communications bus and playback of the recorded simulation. Bus signal vectors are recorded by recorder logic during the simulation, and player logic reads the recorded signal vectors and provides the appropriate bus signals at the appropriate times during playback of the simulation.

摘要翻译： 一种用于演示通信总线仿真的方法和系统。 在各种实施例中，描述了支持记录具有通信总线和记录的仿真的回放的系统的模拟的方法和系统。 总线信号向量由仿真期间的记录器逻辑记录，播放器逻辑读取记录的信号向量，并在模拟回放期间的适当时刻提供适当的总线信号。

公开(公告)号：US07668186B1

公开(公告)日：2010-02-23

申请号：US11369338

申请日：2006-03-07

申请人： Roscoe Conkling Nelson, IV ,  Stacey Secatch ,  Thomas E. Fischaber ,  Tony Viet Nam Le

发明人： Roscoe Conkling Nelson, IV ,  Stacey Secatch ,  Thomas E. Fischaber ,  Tony Viet Nam Le

IPC分类号： H04L12/56

CPC分类号： H04L49/90

摘要： A buffer management system for a data processing system can include a plurality of tokens wherein each token is associated with one of a plurality of buffers, and a plurality of first-in-first-out (FIFO) memories. Each FIFO memory can be associated with a stage of the data processing system and is configured to store at least one of the tokens. The buffer management system also can include control logic configured to determine a state of one or more selected buffers and transfer the token associated with the selected buffer from a source FIFO memory to a target FIFO memory. The target FIFO memory can be selected according to the state of the selected buffer.

摘要翻译： 用于数据处理系统的缓冲器管理系统可以包括多个令牌，其中每个令牌与多个缓冲器中的一个和多个先进先出（FIFO）存储器相关联。 每个FIFO存储器可以与数据处理系统的级相关联，并且被配置为存储至少一个令牌。 缓冲器管理系统还可以包括被配置为确定一个或多个所选择的缓冲器的状态并将与所选择的缓冲器相关联的令牌从源FIFO存储器传送到目标FIFO存储器的控制逻辑。 可以根据所选缓冲区的状态选择目标FIFO存储器。

公开(公告)号：US07852705B1

公开(公告)日：2010-12-14

申请号：US11527887

申请日：2006-09-27

申请人： Tony Viet Nam Le

发明人： Tony Viet Nam Le

IPC分类号： G11C8/02

CPC分类号： G06F12/0646 ,  H03K19/1776

摘要： A method of configuring a plurality of memory elements having selectable dimensions, the method comprising the steps of selecting a width of a data word to be output by a circuit having the plurality of memory elements; selecting a width for memory locations of the plurality of memory elements, the width for the memory location being less than the width of a data word; configuring the plurality of memory elements to have the selected width; and concatenating the outputs for the plurality of memory elements to generate a concatenated output comprising a data word. A circuit for configuring a plurality of memory elements having selectable dimensions is also disclosed.

摘要翻译： 一种配置具有可选尺寸的多个存储元件的方法，所述方法包括以下步骤：选择要由具有所述多个存储元件的电路输出的数据字的宽度; 选择所述多个存储元件的存储器位置的宽度，所述存储器位置的宽度小于数据字的宽度; 将所述多个存储器元件配置为具有所选择的宽度; 并且连接多个存储器元件的输出以产生包括数据字的级联输出。 还公开了一种用于配置具有可选尺寸的多个存储元件的电路。