公开(公告)号：US08547777B2

公开(公告)日：2013-10-01

申请号：US12928989

申请日：2010-12-22

Applicant: Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

Inventor： Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/02

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08

Abstract: A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Abstract translation: 公开了一种用于在DRAM中选择字线驱动器的NOR架构。 用于选择最终字线驱动程序的低，中，高范围内单独解码的地址的完成。 字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

公开(公告)号：US08379428B2

公开(公告)日：2013-02-19

申请号：US12914086

申请日：2010-10-28

Applicant: Hiroyuki Ogawa ,  Akihisa Yamaguchi

Inventor： Hiroyuki Ogawa ,  Akihisa Yamaguchi

IPC: G11C5/06 ,  G11C8/02 ,  H01L27/108

CPC classification number: H01L21/28 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10882 ,  H01L27/10891 ,  H01L27/10894

Abstract: A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.

公开(公告)号：US07715271B1

公开(公告)日：2010-05-11

申请号：US12176592

申请日：2008-07-21

Applicant: Haiming Yu ,  Wei Yee Koay

Inventor： Haiming Yu ,  Wei Yee Koay

IPC: G11C8/02

CPC classification number: H03K19/1776 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C2207/105 ,  H03K19/17744

Abstract: A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.

Abstract translation: 存储单元包括能够以不同数据宽度在存储器阵列中访问数据的宽度解码逻辑。 为了提高存储器访问速度，存储器单元还包括用于以存储器阵列的完整数据宽度访问数据的专用读取输出路径。 专用读输出路径绕过宽度解码逻辑，并将数据从存储器阵列直接提供给数据总线，从而在不需要宽度解码时提供改进的存储器性能。 存储器单元可并入可编程器件中，并且可编程器件配置可以选择读取旁路路径或宽度解码逻辑。 需要宽度解码和改善存储器访问速度的硬件应用可以利用存储器单元之外的附加可编程设备资源来从存储器单元注册全宽数据并将其转换成不同的数据宽度。

公开(公告)号：US07554878B2

公开(公告)日：2009-06-30

申请号：US11511678

申请日：2006-08-29

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: G11C8/02

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C7/227

Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Abstract translation: 同步存储器件，其包括读命令缓冲器，复制电路和延迟电路。 读取命令缓冲器响应读取命令提供读取信号。 复制电路提供传输信号，其相对于反馈时钟信号的时间差基本上与读取命令缓冲器提供读取信号所需的时间相同。 等待时间电路接收读取信号，并响应于传送信号提供相对于读取信号的对应于CAS等待时间的预定时间的差异的等待时间信号。

公开(公告)号：US07420870B2

公开(公告)日：2008-09-02

申请号：US11430199

申请日：2006-05-09

Applicant: Moon-Sook Park ,  Kyu-Hyoun Kim

Inventor： Moon-Sook Park ,  Kyu-Hyoun Kim

IPC: G11C8/02 ,  H03L7/06

CPC classification number: H03L7/0995 ,  H03K3/0315 ,  H03K5/133 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093

Abstract: A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.

Abstract translation: 一种锁相环电路及锁相方法。 相位锁定环电路可以包括接收外部时钟信号和反馈时钟信号的相位检测器，并且当外部时钟信号的相位引导反馈时钟信号的相位并在相位为 外部时钟信号滞后于反馈时钟信号的相位，环路滤波器电路响应于上升信号增加控制电压，并响应于下降信号降低控制电压，以及压控振荡器电路接收控制电压和 直接产生n个（其中n是整数> = 4）内部时钟信号。 相位锁定环路电路还可以包括压控振荡器电路，其包括至少四个环路，接收控制电压并产生多个内部时钟信号。

公开(公告)号：US20080157845A1

公开(公告)日：2008-07-03

申请号：US11776327

申请日：2007-07-11

Applicant: Sun Suk YANG

Inventor： Sun Suk YANG

IPC: G11C8/02 ,  G06F1/04

CPC classification number: G11C8/18 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

Abstract: The present invention relates to a semiconductor memory device having a clock buffer circuit which buffers an external clock to generate an internal clock, wherein the clock buffer circuit comprises a rising clock buffer which buffers an external clock to generate a rising internal clock corresponding to a rising edge of the external clock; and a falling clock buffer which buffers the external clock to generate a falling internal clock corresponding to a falling edge of the external clock, whereby the external signal is input to the internal circuit in synchronization with the rising internal clock and the falling internal clock.

Abstract translation: 本发明涉及具有时钟缓冲电路的半导体存储器件，其缓冲外部时钟以产生内部时钟，其中时钟缓冲电路包括一个上升时钟缓冲器，其缓冲外部时钟以产生对应于上升沿的上升内部时钟 外部时钟的边缘; 以及下降时钟缓冲器，其缓冲外部时钟以产生对应于外部时钟的下降沿的下降的内部时钟，由此外部信号与内部时钟和下降的内部时钟同步地输入到内部电路。

公开(公告)号：US20060146640A1

公开(公告)日：2006-07-06

申请号：US11319912

申请日：2005-12-27

Applicant: Heung Kim

Inventor： Heung Kim

IPC: G11C8/02

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66575 ,  H01L29/78 ,  Y10S438/938

Abstract: A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.

公开(公告)号：US20060083102A1

公开(公告)日：2006-04-20

申请号：US10969149

申请日：2004-10-20

Applicant: Ayman Ghanem ,  Robert Bean

Inventor： Ayman Ghanem ,  Robert Bean

IPC: G11C8/02

CPC classification number: G11C29/74 ,  G06F11/2074 ,  G06F11/2092

Abstract: A redundant data storage system is provided comprising a first controller with top-level control of a first memory space and a second controller with top-level control of a second memory space different than the first memory space. The system is adapted for asynchronously reflectively writing state information by the first controller to the second memory space; alternatively the system is adapted for asynchronously reflectively writing state information by the second controller to the first memory space. A method is provided for operating the redundant data storage system by resolving any inconsistency between the existing state information and a modified state information associated with a state information change request, and for switching control in the redundant data storage system between the controllers.

Abstract translation: 提供了冗余数据存储系统，其包括具有第一存储器空间的顶级控制的第一控制器和具有与第一存储器空间不同的第二存储器空间的顶级控制的第二控制器。 该系统适于将第一控制器的状态信息异步地反映到第二存储器空间; 或者该系统适于将第二控制器的状态信息异步地反映到第一存储器空间。 提供了一种用于通过解决现有状态信息与与状态信息改变请求相关联的修改状态信息之间的任何不一致以及用于控制器之间的冗余数据存储系统中的切换控制来操作冗余数据存储系统的方法。

公开(公告)号：US20060072370A1

公开(公告)日：2006-04-06

申请号：US11205742

申请日：2005-08-17

Applicant: Bong-Jin Kuh ,  Yong-Ho Ha ,  Ji-Hye Yi

Inventor： Bong-Jin Kuh ,  Yong-Ho Ha ,  Ji-Hye Yi

IPC: G11C8/02

CPC classification number: G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  Y10S438/90

Abstract: A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the contact region of the substrate. A phase-changeable material layer pattern is on the lower electrode, and an upper electrode is on the phase-changeable material layer pattern. The insulating interlayer may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the insulating interlayer. A nitride layer may be formed on the insulating interlayer. The lower electrode may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the lower electrode. Methods of forming phase-changeable memory devices are also disclosed.

Abstract translation: 相变型存储器件包括在其上表面具有接触区域的衬底。 衬底上的绝缘中间层具有开口，并且在开口中形成下电极。 下电极具有氮化表面部分并且与衬底的接触区域电接触。 相变材料层图案位于下电极上，上电极位于相变材料层图案上。 绝缘中间层可以具有氮化表面部分，并且相变材料层可以至少部分地在绝缘中间层的氮化表面部分上。 可以在绝缘中间层上形成氮化物层。 下部电极可以具有氮化表面部分，并且相变材料层可以至少部分地位于下部电极的氮化表面部分上。 还公开了形成相变存储器件的方法。

公开(公告)号：US20060072369A1

公开(公告)日：2006-04-06

申请号：US10960950

申请日：2004-10-12

Applicant: Richard Madter ,  Karin Werder ,  Wei Yao Huang

Inventor： Richard Madter ,  Karin Werder ,  Wei Yao Huang

IPC: G11C8/02

CPC classification number: G11C5/141 ,  G06F12/0804 ,  G06F2212/2022 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/0483 ,  G11C16/30 ,  Y02D10/13

Abstract: A system and method for automatically saving the contents of volatile memory in a data processing device on power failure. A secondary power supply is provided, which upon failure of the primary power supply supplies power long enough for all modified information stored in volatile memory to be written to a non-volatile memory device such as NAND flash in an AutoSave procedure. In the preferred embodiment modified sectors in volatile memory are flagged, and only modified sectors with a directory list are written to non-volatile memory during the AutoSave procedure.