公开(公告)号：US10255979B1

公开(公告)日：2019-04-09

申请号：US15916570

申请日：2018-03-09

申请人： Toshiba Memory Corporation

发明人： Yasuhiro Shimura ,  Shinichi Oosera ,  Junichi Kijima ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Tomohiro Oda ,  Keisuke Yonehama

IPC分类号： G11C16/28 ,  G06F12/0893 ,  G11C16/16 ,  G11C16/34

摘要： According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.

公开(公告)号：US10803950B2

公开(公告)日：2020-10-13

申请号：US16420446

申请日：2019-05-23

申请人： Toshiba Memory Corporation

发明人： Yasuhiro Shimura ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Junichi Kijima ,  Keisuke Yonehama ,  Shinichi Oosera ,  Yuki Kanamori ,  Hidehiro Shiga ,  Koki Ueno

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G11C11/56 ,  G11C7/20

摘要： According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.

公开(公告)号：US20190088342A1

公开(公告)日：2019-03-21

申请号：US15916570

申请日：2018-03-09

申请人： Toshiba Memory Corporation

发明人： Yasuhiro SHIMURA ,  Shinichi Oosera ,  Junichi Kijima ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Tomohiro Oda ,  Keisuke Yonehama

IPC分类号： G11C16/28 ,  G06F12/0893 ,  G11C16/34 ,  G11C16/16

摘要： According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.

公开(公告)号：US20190279716A1

公开(公告)日：2019-09-12

申请号：US16420446

申请日：2019-05-23

申请人： Toshiba Memory Corporation

发明人： Yasuhiro Shimura ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Junichi Kijima ,  Keisuke Yonehama ,  Shinichi Oosera ,  Yuki Kanamori ,  Hidehiro Shiga ,  Koki Ueno

IPC分类号： G11C16/08 ,  G11C16/32 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C11/56

摘要： According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.

公开(公告)号：US10347338B2

公开(公告)日：2019-07-09

申请号：US15699370

申请日：2017-09-08

申请人： Toshiba Memory Corporation

发明人： Yasuhiro Shimura ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Junichi Kijima ,  Keisuke Yonehama ,  Shinichi Oosera ,  Yuki Kanamori ,  Hidehiro Shiga ,  Koki Ueno

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G11C11/56 ,  G11C7/20

摘要： According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.