公开(公告)号：US20190198760A1

公开(公告)日：2019-06-27

申请号：US16287753

申请日：2019-02-27

Applicant: Toshiba Memory Corporation

Inventor： Takashi TACHIKAWA ,  Masumi SAITOH

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/147 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a first metal oxide layer that is provided between the first conductive layer and the second conductive layer and includes at least one first metal element selected from the group consisting of aluminum (Al), gallium (Ga), zirconium (Zr), and hafnium (Hf); and a second metal oxide layer that is provided between the first metal oxide layer and the second conductive layer and includes at least one second metal element selected from the group consisting of zinc (Zn), titanium (Ti), tin (Sn), vanadium (V), niobium (Nb), tantalum (Ta), and tungsten (W). The first metal oxide layer includes a third metal element. The third metal element has a lower valence than a metal element having the highest atomic percent in the first metal oxide layer among the at least one first metal element.

公开(公告)号：US20180277759A1

公开(公告)日：2018-09-27

申请号：US15709753

申请日：2017-09-20

Applicant: Toshiba Memory Corporation

Inventor： Takashi TACHIKAWA ,  Masumi SAITOH

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/147 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a first metal oxide layer that is provided between the first conductive layer and the second conductive layer and includes at least one first metal element selected from the group consisting of aluminum (Al), gallium (Ga), zirconium (Zr), and hafnium (Hf); and a second metal oxide layer that is provided between the first metal oxide layer and the second conductive layer and includes at least one second metal element selected from the group consisting of zinc (Zn), titanium (Ti), tin (Sn), vanadium (V), niobium (Nb), tantalum (Ta), and tungsten (W). The first metal oxide layer includes a third metal element. The third metal element has a lower valence than a metal element having the highest atomic percent in the first metal oxide layer among the at least one first metal element.

公开(公告)号：US20190288059A1

公开(公告)日：2019-09-19

申请号：US16110106

申请日：2018-08-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi TACHIKAWA ,  Hidenori MIYAGAWA

IPC: H01L29/04 ,  H01L27/11582 ,  H01L23/528

Abstract: A semiconductor memory device comprises: a substrate; gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer including a first portion extending in the first direction and facing the plurality of gate electrodes, and, a second portion nearer to the substrate than the first portion; a gate insulating film provided between the gate electrode and the first portion of the first semiconductor layer, and, including a memory portion; and, a wiring portion provided between the substrate and the plurality of gate electrodes, connected to the second portion of the first semiconductor layer, and, extending in a second direction crossing the first direction. The wiring portion comprises a second semiconductor layer connected to the second portion of the first semiconductor layer. The second semiconductor layer includes a first crystal grain larger than a thickness in the first direction of the second semiconductor layer.