公开(公告)号：US06297663B1

公开(公告)日：2001-10-02

申请号：US09417659

申请日：1999-10-14

申请人： Toshinobu Matsuoka ,  Yukihiro Seki ,  Tsunehiro Tobita ,  Shinichi Suzuki

发明人： Toshinobu Matsuoka ,  Yukihiro Seki ,  Tsunehiro Tobita ,  Shinichi Suzuki

IPC分类号： H03K1716

CPC分类号： H04L25/028 ,  H04L25/0278 ,  H04L25/0298

摘要： A bus system has a bus constructed of a plurality of signal lines for transmission of signals, first and second terminating resistors provided at both ends of the respective signal lines, first, second and third modules coupled to the bus between the first and second terminating resistors and being each operative to transmit a signal through an output circuit of open drain type, first series resistors inserted in the respective signal lines between the first and second modules, and second series resistors inserted in the respective signal lines between the second and third modules.

摘要翻译： 总线系统具有由多个用于信号传输的信号线构成的总线，设置在各个信号线的两端的第一和第二终端电阻器，耦合到第一和第二终端电阻器之间的总线的第一，第二和第三模块 并且各自操作以通过插入在第一和第二模块之间的相应信号线中的开漏型，第一串联电阻器的输出电路以及插入在第二和第三模块之间的相应信号线中的第二串联电阻来发送信号。