公开(公告)号：US5293489A

公开(公告)日：1994-03-08

申请号：US60719

申请日：1993-05-13

申请人： Toshiyuki Furui ,  Naoto Kaji ,  Gizo Kadaira ,  Kouji Kinoshita

发明人： Toshiyuki Furui ,  Naoto Kaji ,  Gizo Kadaira ,  Kouji Kinoshita

IPC分类号： G06F12/02 ,  G06F13/00

CPC分类号： G06F12/0207

摘要： In a circuit arrangement for use in accessing selected address numbered with a preselected distance left between two adjacent ones of the selected addresses, a control circuit centralizes control operation of a switching network with reference to a reference one of the selected addresses and the preselected distance to make the switching network form internal paths between input and output port sets of the switching network. Alternatively, when ports of a selected one of the input and output port sets are accessed at a predetermined port interval, the control circuit controls the switching network with reference to the predetermined port interval and a reference port selected from the selected port set. A leading port of the other set is determined to be connected to the reference port. A rearranging circuit may be connected to one of the input and output port sets to rearrange an order of the ports of the one port set in consideration of the port distance. The reference and leading ports may be varied in a time division fashion when a conflict of internal paths otherwise occurs in relation to the port distance.

摘要翻译： 在用于访问以所选地址中的两个相邻地址之间留下的预选距离编号的所选地址的电路装置中，控制电路参考所选择的地址中的参考一个和预选的距离来集中控制交换网络的操作， 使交换网络形成交换网络的输入和输出端口集合之间的内部路径。 或者，当以预定的端口间隔访问输入和输出端口组中所选择的一个端口的端口时，控制电路参考预定的端口间隔和从所选择的端口组中选择的参考端口来控制交换网络。 确定另一组的引导端口连接到参考端口。 考虑到端口距离，重排电路可以连接到输入端口组和输出端口组中的一个，以重新排列一个端口组的端口的顺序。 当相对于端口距离而发生内部路径的冲突时，引用端口可以以时分方式变化。

公开(公告)号：US5293604A

公开(公告)日：1994-03-08

申请号：US655947

申请日：1991-02-15

申请人： Gizo Kadaira

发明人： Gizo Kadaira

IPC分类号： G06F12/06 ,  G06F13/42 ,  G06F15/167 ,  G06F12/00

CPC分类号： G06F15/167 ,  G06F13/4243

摘要： In a memory access control device (10) for use in controlling access by at least one address signal to a memory device (11) comprising memory modules each of which comprises a plurality of memory banks, a module checking circuit (16) checks first and second module signals indicative of the memory modules to produce a module coincidence signal when the first and the second module signals coincide with each other. First and second bank access checking circuits (17, 18) are assigned with first and second preselected number of memory modules and check first and second bank address signals indicative of the memory banks and first and second bank access held signals indicative of at least two of the memory banks which should be accessed. The first and the second bank access checking circuits produce first and second bank coincidence signals when the first and the second bank address signals coincide with the first and the second bank access held signals. An access judging circuit (191) alternatingly produces first and second inhibit signals in response to the module coincidence signal. The first and the second inhibit signals are also produced in response to the first and the second bank coincidence signals. An access signal output control circuit (20) inhibits supply of the address signal as first and second address signals to the memory device in response to the first and the second inhibit signals.

摘要翻译： 一种存储器访问控制装置（10），用于通过至少一个地址信号来控制对包括存储器模块（11）的存储器模块的访问，所述存储器模块包括多个存储器组，模块检查电路（16）首先检查 当第一和第二模块信号彼此一致时，指示存储器模块的第二模块信号产生模块符合信号。 第一和第二存储体存取检查电路（17,18）被分配有第一和第二预选数量的存储器模块，并且检查指示存储体的第一和第二存储区地址信号，以及指示存储器组的至少两个 应该访问的记忆库。 当第一和第二存储区地址信号与第一和第二存储体存取保持信号一致时，第一和第二存储体存取检查电路产生第一和第二存储体重合信号。 访问判断电路（191）响应于模块一致信号交替地产生第一和第二禁止信号。 响应于第一和第二组重合信号也产生第一和第二禁止信号。 访问信号输出控制电路（20）响应于第一和第二禁止信号禁止将地址信号作为第一和第二地址信号提供给存储器件。

公开(公告)号：US5404476A

公开(公告)日：1995-04-04

申请号：US31380

申请日：1993-03-09

申请人： Gizo Kadaira

发明人： Gizo Kadaira

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F12/14

CPC分类号： G06F12/1036

摘要： A requesting processor issues an instruction containing a segmented virtual space identifier (VSID) and a shared-access or nonshared-access identifier. A single translation lookaside buffer is divided into TLB partitions which have corresponding directory registers. Each directory register has a first field for storing a VSID and a second field have bit positions respectively assigned to the processors of the system. If the instruction contains a nonshared-access identifier, a directory controller selects one of the registers whose second field contains all vacant bit positions and writes the VSID of the instruction into the register and sets a bit in a position assigned to the requesting processor. The controller detects a register having the same VSID and first and second bits in positions respectively assigned to the master and requesting processors, and resets the second bit. If the instruction contains a shared-access identifier, then the directory controller detects a first register having the same VSID and a bit in a position assigned to the master processor and a second register having the same VSID and a bit in a position assigned to the requesting processor, sets a bit in a position of the first register assigned to the requesting processor, and resets the bit of the second register.

摘要翻译： 请求处理器发出包含分段虚拟空间标识符（VSID）和共享访问或非共享访问标识符的指令。 单个翻译后备缓冲区分为具有相应目录寄存器的TLB分区。 每个目录寄存器具有用于存储VSID的第一字段和分别分配给系统处理器的位位置的第二字段。 如果指令包含非共享访问标识符，则目录控制器选择其第二字段包含所有空位位置的寄存器之一，并将该指令的VSID写入寄存器，并将位置设置在分配给请求处理器的位置。 控制器检测具有相同VSID的寄存器以及分别分配给主设备和请求处理器的位置中的第一和第二位，并且复位第二位。 如果指令包含共享访问标识符，则目录控制器检测到具有相同VSID的位置的第一寄存器和分配给主处理器的位置中的位和具有相同VSID的第二寄存器和分配给 请求处理器将分配给请求处理器的第一寄存器的位置置位，并且复位第二寄存器的位。