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公开(公告)号:US06833582B2
公开(公告)日:2004-12-21
申请号:US10766188
申请日:2004-01-29
申请人: Toshiyuki Mine , Takashi Hashimoto , Senichi Nishibe , Nozomu Matsuzaki , Hitoshi Kume , Jiro Yugami
发明人: Toshiyuki Mine , Takashi Hashimoto , Senichi Nishibe , Nozomu Matsuzaki , Hitoshi Kume , Jiro Yugami
IPC分类号: H01L29792
CPC分类号: H01L29/66833 , G11C16/0466 , H01L21/28282 , H01L29/792
摘要: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.