公开(公告)号：US06833582B2

公开(公告)日：2004-12-21

申请号：US10766188

申请日：2004-01-29

申请人： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

发明人： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

IPC分类号： H01L29792

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/792

摘要： A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

公开(公告)号：US06657248B1

公开(公告)日：2003-12-02

申请号：US09432460

申请日：1999-11-02

申请人： Nozomu Matsuzaki ,  Takashi Kobayashi ,  Hitoshi Kume ,  Toshiyuki Mine ,  Kikuo Kusukawa ,  Norio Suzuki ,  Kenji Takahashi ,  Toshiaki Nishimoto ,  Masataka Kato

发明人： Nozomu Matsuzaki ,  Takashi Kobayashi ,  Hitoshi Kume ,  Toshiyuki Mine ,  Kikuo Kusukawa ,  Norio Suzuki ,  Kenji Takahashi ,  Toshiaki Nishimoto ,  Masataka Kato

IPC分类号： H01L27108

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： There was a problem that sharpening of a substrate and localized increase in the thickness of a gate oxide film become more remarkable as the thickness of the gate oxide film is increased to degrade the gate withstand voltage at the surface edge of shallow groove isolation structure. In the present invention, a bird's beak is disposed at the surface edge of a shallow isolation structure GROX11 just below gate electrode POLY11 and in contact with the gate insulation film HOX1 to form the gate insulation film HOX1 previously. This can ensure normal gate withstand voltage of the MOS transistor and favorable device isolation withstand voltage and increased integration degree simultaneously.

摘要翻译： 存在栅极氧化膜的厚度增加以使栅极氧化膜的厚度急剧增加并且栅极氧化膜的厚度局部增加以降低浅沟槽隔离结构的表面边缘处的栅极耐受电压的问题。 在本发明中，将鸟嘴设置在正好位于栅电极POLY11正下方的浅隔离结构GROX11的表面边缘处，并且与栅极绝缘膜HOX1接触以预先形成栅极绝缘膜HOX1。 这可以确保MOS晶体管的正常栅极耐受电压，并且同时具有良好的器件隔离耐受电压和增加的积分度。

公开(公告)号：US06617632B2

公开(公告)日：2003-09-09

申请号：US10005300

申请日：2001-12-07

申请人： Yasuhiro Taniguchi ,  Kazuyoshi Shiba ,  Nozomu Matsuzaki ,  Hidenori Takada ,  Hitoshi Kume ,  Shoji Shukuri

发明人： Yasuhiro Taniguchi ,  Kazuyoshi Shiba ,  Nozomu Matsuzaki ,  Hidenori Takada ,  Hitoshi Kume ,  Shoji Shukuri

IPC分类号： H01L27108

CPC分类号： H01L27/11526 ,  G11C16/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-through stopper layer which is adjacent to the first semiconductor region and formed by introducing a first conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially higher than the channel region in impurity concentration, and wherein the source regions and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns, word lines some of which constitute the control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, a voltage is applied to at least one word line, which is set so as to serve as a selected word line, and when carriers are stored in a floating gate electrode of each selected memory cell, a negative voltage is applied to other non-selected word lines other than the selected word line.

公开(公告)号：US07130223B2

公开(公告)日：2006-10-31

申请号：US11251963

申请日：2005-10-18

申请人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

发明人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

摘要： Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

摘要翻译： 提高了非易失性半导体存储器件的特性。 存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。 通过向具有源极区域MS和漏极区域MD的存储单元的选择栅极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子， 选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。

公开(公告)号：US06972997B2

公开(公告)日：2005-12-06

申请号：US10743783

申请日：2003-12-24

申请人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

发明人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

IPC分类号： G11C11/34 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

摘要： Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

摘要翻译： 提高了非易失性半导体存储器件的特性。 存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。 通过向具有源极区域MS和漏极区域MD的存储单元的选择栅极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子， 选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。

公开(公告)号：US20060050557A1

公开(公告)日：2006-03-09

申请号：US11251963

申请日：2005-10-18

申请人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

发明人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

摘要： Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

公开(公告)号：US08482997B2

公开(公告)日：2013-07-09

申请号：US13366329

申请日：2012-02-05

申请人： Satoru Hanzawa ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Saen

发明人： Satoru Hanzawa ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Saen

IPC分类号： G11C7/00 ,  G11C11/00 ,  H01L21/00

CPC分类号： G01R31/31715 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72 ,  Y10T29/49169

摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。

公开(公告)号：US20120075926A1

公开(公告)日：2012-03-29

申请号：US13312620

申请日：2011-12-06

申请人： Satoru HANZAWA ,  Hitoshi Kume

发明人： Satoru HANZAWA ,  Hitoshi Kume

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0023 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72

摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。

公开(公告)号：US07996735B2

公开(公告)日：2011-08-09

申请号：US12469778

申请日：2009-05-21

申请人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

发明人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

IPC分类号： G11C29/00

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

公开(公告)号：US07468913B2

公开(公告)日：2008-12-23

申请号：US11822120

申请日：2007-07-02

申请人： Tetsufumi Kawamura ,  Hitoshi Kume ,  Tsuyoshi Arigane

发明人： Tetsufumi Kawamura ,  Hitoshi Kume ,  Tsuyoshi Arigane

IPC分类号： G11C16/00

CPC分类号： G11C16/0416 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/3427 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568

摘要： A highly-reliable semiconductor device is realized. For example, each memory cell of a nonvolatile memory included in the semiconductor device is configured to include a source and a drain formed in a P-well, a memory node which is formed on the P-well between the source and the drain via a tunnel insulator and is insulated from its periphery, and a control gate formed on the memory node via an interlayer insulator. When a programming operation using channel hot electrons is to be performed in such a configuration, the P-well is put into an electrically floating state.