Header range check hash circuit
    1.
    发明授权
    Header range check hash circuit 有权
    标题范围检查散列电路

    公开(公告)号:US07346059B1

    公开(公告)日:2008-03-18

    申请号:US10657497

    申请日:2003-09-08

    CPC分类号: H04L12/4625

    摘要: A technique efficiently searches a hash table containing a plurality of “ranges.” In contrast with previous implementations, the technique performs fewer searches to locate one or more ranges stored in the hash table. To that end, the hash table is constructed so each hash-table entry is associated with a different linked list, and each linked-list entry stores, inter alia, “signature” information and at least one pair of values defining a range associated with the signature. The technique modifies the signature based on the results of one or more preliminary range checks. As a result, the signature's associated ranges are more evenly distributed among the hash table's linked lists. Thus, the linked lists are on average shorter in length, thereby enabling faster and more efficient range searches. According to an illustrative embodiment, the technique is applied to flow-based processing implemented in an intermediate network node, such as a router.

    摘要翻译: 技术有效地搜索包含多个“范围”的散列表。 与先前的实现相比,该技术执行较少的搜索来定位存储在散列表中的一个或多个范围。 为此,构建哈希表,使得每个散列表条目与不同的链表相关联,并且每个链表列表条目尤其存储“签名”信息和至少一对定义与 签名。 该技术基于一个或多个初步范围检查的结果修改签名。 因此,签名的关联范围在哈希表的链表之间更均匀地分布。 因此,链表的长度平均更短,从而实现更快更有效的范围搜索。 根据说明性实施例,该技术被应用于在诸如路由器的中间网络节点中实现的基于流的处理。

    Memory efficient hashing algorithm
    2.
    发明申请
    Memory efficient hashing algorithm 审中-公开
    内存高效散列算法

    公开(公告)号:US20050171937A1

    公开(公告)日:2005-08-04

    申请号:US10769941

    申请日:2004-02-02

    IPC分类号: G06F17/30

    CPC分类号: G06F16/9014

    摘要: A technique efficiently searches a hash table. Conventionally, a predetermined set of “signature” information is hashed to generate a hash-table index which, in turn, is associated with a corresponding linked list accessible through the hash table. The indexed list is sequentially searched, beginning with the first list entry, until a “matching” list entry is located containing the signature information. For long list lengths, this conventional approach may search a substantially large number of list entries. In contrast, the inventive technique reduces, on average, the number of list entries that are searched to locate the matching list entry. To that end, list entries are partitioned into different groups within each linked list. Thus, by searching only a selected group (e.g., subset) of entries in the indexed list, the technique consumes fewer resources, such as processor bandwidth and processing time, than previous implementations.

    摘要翻译: 一种技术有效地搜索哈希表。 常规地,预定的一组“签名”信息被散列以产生哈希表索引,该哈希表索引又与通过散列表可访问的对应链表相关联。 依次搜索索引列表,从第一个列表条目开始,直到包含签名信息的“匹配”列表条目为止。 对于长列表长度,这种常规方法可以搜索大量的列表条目。 相比之下,本发明技术平均减少了搜索以定位匹配列表条目的列表条目的数量。 为此,列表条目在每个链接列表中被分成不同的组。 因此,通过仅搜索索引列表中的选择的组(例​​如,子集)条目,该技术比先前的实现消耗更少的资源,例如处理器带宽和处理时间。

    Method and apparatus for synchronizing use of buffer descriptor entries
    3.
    发明申请
    Method and apparatus for synchronizing use of buffer descriptor entries 有权
    用于同步使用缓冲区描述符条目的方法和装置

    公开(公告)号:US20080005296A1

    公开(公告)日:2008-01-03

    申请号:US11430116

    申请日:2006-05-08

    IPC分类号: G06F15/173

    摘要: Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

    摘要翻译: 用于同步数据的使用的技术,例如通过网络发送的分组,包括接收指示由DMA控制器拥有的特定缓冲器描述符的专用索引数据,用于在数据端口和对应的存储器缓冲器之间移动数据。 写命令被放置在存储器交换队列上,以将所有者更改为不同的处理器,并且私有索引数据被递增。 确定公共索引,其指示所有者最近更改为处理器并且已知对于处理器可见的不同缓冲器描述符。 响应于从处理器接收到更改为处理器所有权的最新缓冲器描述符的请求,将公共索引数据发送到处理器。 基于公共索引数据,处理器与保证由处理器拥有的缓冲区描述符交换数据。

    TDM format optimized for multiple high speed links to a communications controller
    4.
    发明授权
    TDM format optimized for multiple high speed links to a communications controller 失效
    TDM格式针对通信控制器的多个高速链路进行了优化

    公开(公告)号:US06754242B1

    公开(公告)日:2004-06-22

    申请号:US09619212

    申请日:2000-07-19

    IPC分类号: H04J302

    CPC分类号: H04J3/1623 H04J3/0685

    摘要: A highly interleaved Time Division Multiplexing (TDM) format allows for high data density transfer for a given port at a communications controller. The port is coupled to a Time Slot Assigner (TSA) that will steer the provisioned timeslots of the interleaved TDM data to appropriate Serial Communication Controllers (SCCs), both which are internal to the communications controller. Entries in a Serial Interface Random Access Memory (SI RAM) that is coupled to the TSA and a lookup memory in a clock gapping function block located at a TDM interleaving circuit, are programmed by the communication controller to facilitate the TSA in steering the timeslots.

    摘要翻译: 高度交错的时分复用(TDM)格式允许通信控制器上给定端口的高数据密度传输。 该端口耦合到时隙分配器(TSA),该时隙分配器(TSA)将将交织的TDM数据的所提供的时隙引导到通信控制器内部的适当的串行通信控制器(SCC)。 串行接口中的条目通过通信控制器对耦合到TSA的时钟间隔功能块中的TSA和查找存储器中的随机存取存储器(SI RAM)进行编程,以便于TSA在转向时隙。

    Method and apparatus for synchronizing use of buffer descriptor entries for shared data packets in memory
    5.
    发明授权
    Method and apparatus for synchronizing use of buffer descriptor entries for shared data packets in memory 有权
    用于同步使用存储器中共享数据包的缓冲区描述符条目的方法和装置

    公开(公告)号:US07461180B2

    公开(公告)日:2008-12-02

    申请号:US11430116

    申请日:2006-05-08

    IPC分类号: G05F13/00 G06F15/173

    摘要: Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

    摘要翻译: 用于同步数据的使用的技术,例如通过网络发送的分组,包括接收指示由DMA控制器拥有的特定缓冲器描述符的专用索引数据,用于在数据端口和对应的存储器缓冲器之间移动数据。 写命令被放置在存储器交换队列上,以将所有者更改为不同的处理器,并且私有索引数据被递增。 确定公共索引,其指示所有者最近更改为处理器并且已知对于处理器可见的不同缓冲器描述符。 响应于从处理器接收到更改为处理器所有权的最新缓冲器描述符的请求,将公共索引数据发送到处理器。 基于公共索引数据,处理器与保证由处理器拥有的缓冲区描述符交换数据。